XRT83L38 Datasheet, PDF (58/91 Pages) Exar Corporation – OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
TABLE 21: MICROPROCESSOR REGISTER #2, BIT DESCRIPTION
D4
TXTEST0_n Transmit Test Pattern bit 0: See description of bit D6 for the R/W
0
function of this bit.
D3
TXON_n Transmitter ON: Writing a “1” into this bit location turns on the R/W
0
Transmit and Receive Sections of channel n. Writing a “0”
shuts off the Transmit Section of channel n. In this mode,
TTIP_n and TRING_n driver outputs will be tri-stated for power
reduction or redundancy applications.
D2
LOOP2_n Loop-Back control bit 2: This bit together with the LOOP1
and LOOP0 bits control the Loop-Back modes of the chip
according to the following table:
LOOP2
0
1
1
1
1
LOOP1
X
0
0
1
1
LOOP0 Loop-Back Mode
X
No Loop-Back
0
Dual Loop-Back
1
Analog Loop-Back
0
Remote Loop-Back
1
Digital Loop-Back
D1
LOOP1_n Loop-Back control bit 1: See description of bit D2 for the
R/W
0
function of this bit.
D0
LOOP0_n Loop-Back control bit 0: See description of bit D2 for the
R/W
0
function of this bit.
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