XRD98L56 Datasheet, PDF (4/35 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 10-Bit A/D

XRD9855/9856
XRD98L55/98L56
PIN DESCRIPTION – 48 pin TQFP (CONT’D)
Pin #
Symbol
Description
16
OE
Digital Output Enable (Three-State Control). Pull OE low to enable output
drivers. Pull OE high to put output drivers in high impedance state.
17
V_DD
18
EnableCal
19
GND
Analog Power Supply.
Calibration Enable. Automatic offset calibration control.
Analog Ground.
20
TESTVIN
ADC Test Input & PGA Test Output.
21
STBY1
Standby Control 1. Pull low to put chip in power down mode.
22
STBY2
Standby Control 2. Short to STBY1 pin if not using TESTVIN pin.
23
RESET
Chip Reset. Pull high to reset all internal registers.
24
SCLK
Shift Clock. Shift register latches SDI data on rising edges of SCLK.
25
NC
No Connect.
26
LOAD
Data Load. Rising edge loads data from shift register to internal register. Load
must be low to enable shift register.
27
SDI
Serial Data Input.
28
V_RT
29
V_RTO
30
V_DD
31
In_Neg
Top ADC Reference. Voltage at V_RT sets full-scale of ADC.
Internal Bias for V_RT. Short V_RT to V_RTO to use internal reference voltage.
Analog Power Supply.
CDS Inverting Input. Connect via capacitor to CCD video output.
32
In_Pos
CDS Non-inverting Input. Connect via capacitor to CCD supply.
33
GND
Analog Ground.
34
V_RBO
35
V_RB
36
NC
Internal Bias for V_RB. Short V_RB to V_RB0 to use internal reference voltage.
Bottom ADC Reference. Voltage at V_RB sets zero scale of the ADC.
No Connect.
37
CLAMP
CDS DC Restore Clamp. Clamps In_Pos & In_Neg to internal bias voltage.
38
SHD
CDS Clock. Controls sampling of the pixel video level.
39
SHP
CDS Clock. Controls sampling of the pixel black level.
40
RSTCCD
CCD Reset Pulse Disconnect. Used to decouple CDS during the reset pulse.
41
GND
Analog Ground.
42
CLK_POL
Clock Polarity. Controls the polarity of SHP, SHD & CLAMP.
43
V_DD
44
SYNC
45
UNDER
46
DBO
Analog Power Supply.
Digital output for Exar test purposes only. No connect.
Under Range Output Bit. UNDER goes high to indicate the ADC input voltage
is less than V_RB.
ADC Output. LSB
47
DB1
ADC Output.
48
NC
No Connect.
Rev. 1.01
4