XRD98L56 Datasheet, PDF (15/35 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 10-Bit A/D

XRD9855/9856
XRD98L55/98L56
SDI
SCLK
LOAD
ADDRESS
AD1 AD0
(MSB)
Bit 7
Bit 6
TSET=10ns min.
DATA
Bit 5 Bit 4 Bit 3
Data Shifts on
Rising Edges
Bit 2
Bit 1
(LSB)
Bit 0
TSET=10ns min.
TSC=50ns min.
TSET=10ns min.
Load Internal Register
Figure 7. Serial Port Timing Diagram
Name
Gain
Offset
Mode
Delay
Address
AD1 AD0
0
0
0
1
1
0
1
1
bit 7
Gain[7]
Offset[7]
V[1]
Dp[2]
bit 6
Gain[6]
Offset[6]
V[0]
Dp[1]
bit 5
Gain[5]
Offset[5]
M3
Dp[0]
Data
bit 4
bit 3
Gain[4] Gain[3]
Offset[4] Offset[3]
M2
Test3
Dd[2]
Dd[1]
bit 2
Gain[2]
Offset[2]
Test2
Dd[0]
bit 1
Gain[1]
Offset[1]
M1
Dr[1]
bit 0
Gain[0]
Offset[0]
Reset
Dr[0]
Table 2. Serial Interface Register Address Map
bit 7
bit 6
bit 5
bit 4
bit 3
Gain [7:0]
0 0 0 0 0 0 0 0 - minimum gain (6dB) *
1 1 1 1 1 1 1 1 - maximum gain (38 dB)
bit 2
bit 1
bit 0
Table 3. Gain Register Bit Assignment
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
Offset [7:0]
0 0 0 0 0 0 0 0 - do not use
0 0 0 0 0 0 0 1 - do not use
0 0 0 0 0 0 1 0 - minimum offset code
0 0 0 0 1 0 0 0 - default offset code, typical offset code 00100000
0 0 1 1 1 1 1 1 - maximum offset code
Table 4. Offset Register Bit Assignment
bit 1
bit 0
Rev. 1.01
15