XRD98L56 Datasheet, PDF (14/35 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 10-Bit A/D

XRD9855/9856
XRD98L55/98L56
IN_POS
IN_NEG
CDS
PGA
ADC
10
DB[9:0]
XOE
Up/Down
Counter
A
A-B
B
EnableCal
State
Machine
Offset Reg
ADCLOCK
Figure 5. Automatic Offset Calibration Loop
Manual Global Offset, V [1:0]
In some systems the black level offset can be larger
than the Automatic Offset Calibration Range. The
XRD9855/XRD9856 provide a user programmable glo-
bal offset adjustment which adds to the automatic
offset calibration. The global offset is applied at the
PGA input, so it’s input referred value does not change
with PGA gain code, see Figure 6. The magnitude of the
global offset is controlled by bits V[1:0] in the mode
register. (See Table 1.)
CCD
Input _{CDS + PGA}
ADC
DB[9:0]
V[1:0]
Manual
Global Offset
Automatic
Offset
Calibration
Figure 6. Manual Global Offset & Automatic
Offset Calibration
V[1]
V[0]
0
0
0
1
1
0
1
1
Offset
0mV
25mV (default)
50mV
75mV
Table 1. Manual Global
Offset Programming
Serial Interface
A three wire serial interface, (LOAD, SCLK, and SDI),
is used to program the PGA gain register, the Calibra-
tion offset register, the Mode control register, and the
Aperture delay register. The shift register is 10 bits
long. The first two bits loaded are the address bits that
determine which of the four registers to update. The
following eight bits are the data bits (MSB first, LSB
last). When LOAD is high SCLK is internally disabled.
Since SCLK is gated by LOAD, SCLK can be a
continuously running clock signal, but this will increase
system noise. To enable the shift register the LOAD pin
must be pulled low. The data at SDI is strobed into the
shift register on the rising edges of SCLK. When the
LOAD signal goes high the data bits will be written to the
register selected by the address bits (see Figure 7).
Rev. 1.01
14