XRD98L56 Datasheet, PDF (20/35 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 10-Bit A/D

XRD9855/9856
XRD98L55/98L56
Active Video Pixels
on Optical Black Lines
CCD
Signal
Line N
OB*
Pixels
Vertical
Shift
Line N+1
Dummy &
OB*
Pixels
Active Video
Pixels on OB line
EnableCal
Clamp
RSTCCD
SHP
SHD
CLK_POL=Low
* Note: OB = Optically Black or Shielded pixels.
Figure 11. CCD Line Timing with CLK_POL = 0, M2 = 0
No RSTCCD Pulse Timing, M2 = 1
To help simplify the timing required to drive the
XRD9855/XRD9856 we have included a timing mode
which does not require an active signal for RSTCCD.
To use this timing, bit M2 in the timing mode register
must be set high.
In this timing mode, RSTCCD must be kept low. No
changes are required for the timing of the SHP and SHD
signals. The polarity of SHP, SHD and Clamp are still
controlled by the CLK_POL pin. The digital outputs
change on the sampling edge of SHD (see Figure 12).
This mode can be used with both the XRD4460 and
XRD9853 compatible timing as described in the Line
Timing section. Data output DB[9:0} is delayed as SHD
is delayed with the delay feature AD[1:0] = [1,1].
CCD Signal
Pixel N
1
RSTCCD ₀
1
SHP ₀
SHD
1
0
1
DB[9:0] ₀
Data N-4
Data N-3
Data N-2
Data N-1
Rev. 1.01
Figure 12. Timing for no RSTCCD Pulse,
M2=1 & CLK_POL=1, RSTCCD=0
20
Data N