XRD98L56 Datasheet, PDF (22/35 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 10-Bit A/D

XRD9855/9856
XRD98L55/98L56
Active Pixels
Optically Black Pixels
(OB)
N+1
N
Figure 13. Typical Outline of an Area Array
CCD.
The CCD has many OB pixels available for use in
calibration. Some are available at the start and end of
each line while whole lines of OB pixels are available at
the top and bottom of the array.
The XRD9855 and XRD9856 take advantage of the
large number of OB pixels available at the top and
bottom of the CCD array to perform calibration before
any active pixels are processed.
The XRD9855 and XRD9856 use a digital feedback
loop to achieve auto-calibration. The output of the ADC
and a desired dark code programmed in the offset
register are compared during the OB pixel output from
the CCD. The recommended offset register value is 32
decimal. The difference determines whether the offset
adjustment DAC increments or decrements. This ad-
justs the offset of the PGA to achieve the desired ADC
output code for a dark pixel input.
The first adjustment requires 8 cycles of SHP/SHD
clocks but every subsequent adjustment requires only
6 cycles: 1 cycle for CDS, 3 cycles for A/D conversion,
1 cycle for logic, and 1 cycle for DAC update, see Figure
14. When Enable_Cal pin is low, the offset calibration
logic is disabled, and the current state of the offset DAC
is held constant.
The XRD9855 and XRD9856 calibration time depends
on the calibration method and the number of OB pixels
available. The time required to achieve calibration, in
frame calibration, depends on the number of OB pixels
present in each line.
Using Frame calibration, calibration can be achieved
after several lines depending upon the number of OB
pixels at the top or bottom of an array. Enable_Cal must
be generated by the timing generator to properly frame
the optical black lines.
INNEG
RSTCCD
OB Pixels
SHP
SHD
Enable_Cal
State
0
RESET
ADC Sample point
ADC Sample point
1
2
3
4
5
6
7
2
3
4
5
6
7
Enable CDS ADC ADC ADC Digcomp/ DAC CDS ADC ADC ADC Digcomp/ DAC
Cal on samples converts converts converts accum Update samples converts converts converts accum Update
settle input
input
0
RESET
Figure 14. XRD9855 and XRD9856 Offset Calibration Timing, M3 = 1
Rev. 1.01
22