XRD98L56 Datasheet, PDF(16/35 Page) Exar Corporation – CCD Image Digitizers with CDS, PGA and 10-Bit A/D

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XRD98L56 Datasheet, PDF (16/35 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 10-Bit A/D

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XRD9855/9856

XRD98L55/98L56

bit 7

bit 6

V[1:0]

0 0 - 0mV offset

0 1 - 25mV offset*

1 0 - 50mV offset

1 1 - 75mV offset

bit 5

0 - Clamp only*

1 - Clamp & Cal

bit 4

bit 3

bit 2

Test3

Test2

0 - RSTCCD* 0 - TestVin off* 0 - test off*

1 - no RSTCCD 1 - TestVin on 1 - factory test

bit 1

0 - auto detect*

1 - manual

bit 0

Reset

0 - normal*

1 - reset

Table 5. Mode Register Bit Assignment

bit 7

bit 6

Dp[2:0]

0 0 0 - SHP min delay *

1 1 1 - SHP max delay

bit 5

bit 4

bit 3

bit 2

Dd[2:0]

0 0 0 - SHD min delay *

1 1 1 - SHD max delay

bit 1

bit 0

Dr[1:0]

0 0 - RSTCCD min delay *

1 1 - RSTCCD max delay

Note:

* Indicates default value

Table 6. Delay Register Bit Assignment

SHP, SHD and RSTCCD Signals, M2 = 0

The SHP input to the XRD9855/XRD9856 determines

when the Black level of each pixel is sampled. For

CLK_POL=high timing mode, the black level is

sampled on the falling edge of SHP. For

CLK_POL=low timing mode, the black level is sampled

on the rising edge of SHP.

The sampling edge of SHP should be positioned so that

it samples the pixel black level at a stable and repeat-

able point. The black level should be sampled after the

CCD output has had time to settle from the reset pulse

and before the output transitions to the video level (see

Figure 8). Aperture delay TBK needs to be taken into

consideration when positioning the sampling edge of

SHP (see Figure 8). This aperture delay is the time

from the sampling edge of SHP to the time the pixel

black level is actually sampled by the CDS. The

correct positioning of SHP will be 6-7 ns prior to where

the black level has adequately settled. This is typically

just before the CCD signal starts the transition to the

video level.

The SHD input to the XRD9855/XRD9856 determines

when the Video level of each pixel is sampled. For

CLK_POL=high timing mode, the video level is

sampled on the falling edge of SHD. For

CLK_POL=low timing mode, the video level is sampled

on the rising edge of SHD.

Rev. 1.01

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