XRD98L56 Datasheet, PDF (26/35 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 10-Bit A/D

XRD9855/9856
XRD98L55/98L56
CCD
Input
Clamp & EnableCal Mode
CDS PGA
ADC
DB[9:0]
Clk_Pol
Clamp
EnableCal
DC Restore
switch
bias
Offset
Calibration
Figure 20. Clamp & Enable Cal Mode (XRD9853 Compatible),
M1=1, M3=3
Stand-by Mode (Power Down)
The STBY1 and STBY2 pins are used to put the chip
into the Stand-by or Power down mode. In this mode
all sampling and conversion stops, The digital outputs
are put into the high impedance mode, and the power
supply current will drop to less than 50µA.
For most applications STBY1 and STBY2 should be
connected together and treated as a single control pin.
If an application uses the TestVin pin to access the
PGA output or the ADC input then STBY1 and STBY2
must be separately controlled, see the truth table
below.
CDS/
STBY2 STBY1 PGA
0
0
Off
1
0
On
0
1
Off
1
1
On
ADC
Off
Off
On
On
Clock Digital
Inputs Outputs
Off High-z
On High-z
On
On
On
On
Table 12. Stand-by Truth Table
Rev. 1.01
26