XRD98L56 Datasheet, PDF (19/35 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 10-Bit A/D

XRD9855/9856
XRD98L55/98L56
CDS Clock Polarity
The CLK_POL pin is used to determine the polarity of
the CDS clocks (SHD, SHP, CLAMP). See Figures 10
& 11, and Tables 7 & 8.
Event
Action
↑RSTCCD
↓RSTCCD
Disconnect CDS Inputs from Reset
Noise
Connect CDS Inputs and Track Black
Level
↓SHP
↓SHD
Hold Black Level and Track Video Level
Hold Video Level
↑SHP/SHD No Action
Clamp High Activate DC Restore Clamp
Enable_Cal Activate Offset Calibration
High
Event
↑RSTCCD
↓RSTCCD
↑SHP
↑SHD
Action
Disconnect CDS Inputs from Reset
Noise
Connect CDS Inputs and Track Black
Level
Hold Black Level and Track Video Level
Hold Video Level
↓SHP/SHD No Action
Clamp Low Activate DC Restore Clamp
Enable_Cal Activate Offset Calibration
High
Table 7. Timing Event Description
Table Valid for CLK_POL=1, M2=0
Table 8. Timing Event Description
Table Valid for CLK_POL=0, M2=0
Line N
Active Video
pixels on
OB LINES
OB*pixels
CCD Signal
EnableCal
Clamp
RSTCCD
SHP
SHD
Vertical Shift
Line N+1
Dummy &
OB*pixels
Active Video
pixels on
OB LINES
* Note: OB = Optically Black or Shielded pixels.
Rev. 1.01
Figure 10. CCD Line Timing, CLK_POL= 1, M2 = 0
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