XRD98L56 Datasheet, PDF (21/35 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 10-Bit A/D

XRD9855/9856
XRD98L55/98L56
Programmable Aperture Delays
Dp[2:0], Dd[2:0], Dr[1:0]
To help fine tune the pixel timing, the XRD9855/
XRD9856 allows the system to adjust the aperture
delays associated with SHP (T_BK), SHD (T_VD) and
RSTCCD (T_RST) by programming the Aperture Delay
serial port register. On power up these three aperture
delays are set to their minimum values.
The SHP aperture delay is set by bits Dp[2:0]. Each
LSB adds approximately 2ns of delay. The SHD
aperture delay is set by bits Dd[2:0]. Each LSB adds
approximately 2ns of delay. The RSTCCD aperture
delay is set by bits Dr[1:0]. Each LSB adds approxi-
mately 4ns of delay.
Dp[2] Dp[1] Dp[0]
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
SHP Aperture
Delay T_BK (typ)
6ns (default)
8ns
10ns
12ns
14ns
16ns
18ns
20ns
Table 9. Programmable SHP Delays
Dd[2] Dd[1] Dd[0]
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
SHD Aperture
Delay T_VD (typ)
5ns (default)
7ns
9ns
11ns
13ns
15ns
17ns
19ns
Table 10. Programmable SHD Delays
Dr[1] Dr[0]
0
0
0
1
1
0
1
1
RSTCCD Aperture
Delay T_RST (typ)
3ns (default)
7ns
11ns
15ns
Table 11. Programmable RSTCCD Delays
Line Timing with Frame Calibration
At the beginning and/or end of every CCD frame there
are a number of Optical black lines. The XRD9855/
XRD9856 uses the output from these pixels for the DC
Restore Clamp and Black Level Offset Calibration
functions. These functions are controlled by the Clamp
and/or EnableCal pins.
The XRD9855/XRD9856 is designed to be compatible
with the Clamp Only timing of the XRD4460 or the
Clamp & EnableCal timing of the XRD9853. On power
up the chip will automatically detect which timing is
being used and make the necessary internal adjust-
ments. If EnableCal is high when Clamp is active, then
"Clamp Only" timing is selected (M3=0). If EnableCal
is low when Clamp is active, then "Clamp & Cal" timing
is selected (M3=1). If required, the automatic detection
function can be disabled through the serial port, and the
chip can be forced into one of the two timing modes by
programming mode register bits M3 & M1. Frame
clibration however, can only be used with m3=0.
To maximize dynamic range in the dark areas of an
image the PGA black level output must be equal to
the bottom reference voltage of the ADC. This
ensures that a dark pixel input corresponds to a
desired minimum code output from the XRD9855 and
XRD9856.
The XRD9855 and XRD9856 use the Optically Black
(OB) pixels on a CCD array to calibrate for itself and
the CCD. Figure 13 shows the outline of a typical
CCD. The shaded region on the outside of the array
indicates the position of the optically black (OB)
pixels. The center region indicates the position of the
active pixels used for an image.
Rev. 1.01
21