XRD98L56 Datasheet, PDF (25/35 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 10-Bit A/D

XRD9855/9856
XRD98L55/98L56
Clamp & EnableCal Timing (XRD9853 Compatible)
M1=1, M3=1
In this mode EnableCal must be active during the large
number of Optical Black pixels (usually at the end of
each CCD line or at the start of a frame), Clamp should
be active during the Dummy pixels (usually at the
beginning of each CCD line).
The EnableCal pin (always active high) directly con-
trols the calibration logic.
The Clamp pin (polarity determined by CLK_POL)
controls only the DC restore switch at the CDS input.
EnableCal and Clamp must not be active at the same
time. Clamp must be used every line.
The chip can be forced into this timing mode by
programming the Mode control register bits M1=1 and
M3=1.
Line N
CCD Signal
EnableCal
Clamp
RSTCCD
SHP
SHD
Signal
Pixels
OB* Pixels
Min. 8 OB Pixels
Line N+1
Vertical Shift
(Horizontal Clocking Off)
Dummy &
OB Pixels
Signal
Pixels
Min. 2 Pixels
* Note: OB = Optically Black or Shielded Pixels.
Figure 19. Clamp & EnableCal Timing, CLK_POL=1, M1=1, M3=1, M2=0
Rev. 1.01
25