XRD98L56 Datasheet, PDF (13/35 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 10-Bit A/D

XRD9855/9856
XRD98L55/98L56
Analog-to-Digital Converter
The analog-to-digital converter is based upon a two-
step sub-ranging flash converter architecture with a
built in track and hold input stage. The ADC conversion
is controlled by an internally generated signal, ADCLK
(see Figure 3). The ADC tracks the output of the CDS/
PGA while ADCLK is high and holds when ADCLK is
low. This allows maximum time for the CDS/PGA
output to settle to its final value before being sampled.
The conversion is then performed and the parallel
output is updated, after a 2.5 cycle pipeline delay, on
the rising edge of RSTCCD. The pipeline delay of the
entire XRD9855/XRD9856 is 4 clock cycles.
The internal reference values are set by a resistor
divider between V_DD and GND. To enable the internal
reference, connect V_RTO to V_RT and connect V_RBO to
V_RB. To maximize the performance of the XRD9855/
XRD9856, the internal references should be used and
decoupled to GND. Although the internal references
have been set to maximize the performance of the
CDS/PGA channel, some applications may require
other reference values. To use external references,
drive the V_RT pin directly with the desired voltage.
Connect V_RB to V_RBO. Do not drive V_RB directly. The
ADC parallel output bus is equipped with a high imped-
ance capability, controlled by OE. The outputs are
enabled when OE is low.
Automatic Offset Calibration, Offset [7:0]
To get the maximum color resolution and dynamic
range, this part uses a digital controlled offset calibra-
tion system to compensate for external offset in the
CCD signal as well as internal offsets of the CDS, PGA
and ADC.
The calibration is performed every frame when the CCD
outputs the Optical Black pixels, please see the
section on Frame Timing. The Calibration logic com-
pares the ADC output to the value stored in the serial
port offset register, and increments or decrements the
offset adjust DAC to make the ADC code equal to the
code in the offset register. The first adjustment re-
quires 8 pixels, then 6 pixels for subsequent adjust-
ments. The offset register is 8 bits wide. Two MSBs set
to 00 are added when compared to the 10-bit ADC code.
After power-up the part may require up to 264 adjust-
ments to converge on the proper offset. These adjust-
ments can be made over many lines or frames. For
example, with 20 optical black pixels per line, the
calibration will make 3 adjustments per line, and initial
convergence will require at most 88 lines.
Rev. 1.01
Graph 1. XRD9855 Typical Vdrk (CCD Offset)
Calibration Range @ 25°C
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