W77E532 Datasheet, PDF (73/86 Pages) Winbond – 8 BIT MICROCONTROLLER

W77E532/W77E532A
18.3.2 MOVX Characteristics Using Strech Memory Cycle
PARAMETER
SYMBOL
Data Access ALE Pulse Width
Address Hold After ALE Low
for MOVX write
RD Pulse Width
t_LLHL2
t_LLAX2
t_RLRH
WR Pulse Width
t_WLWH
RD Low to Valid Data In
Data Hold after Read
Data Float after Read
t_RLDV
t_RHDX
t_RHDZ
ALE Low to Valid Data In
t_LLDV
Port 0 Address to Valid Data In t_AVDV1
ALE Low to RD or WR Low
Port 0 Address to RD or WR
Low
t_LLWL
t_AVWL
VARIABLE
CLOCK MIN.
1.5t_CLCL – 5
2.0t_CLCL – 5
0.5t_CLCL – 5
2.0t_CLCL – 5
t_MCS – 10
2.0t_CLCL – 5
t_MCS – 10
0
0.5t_CLCL – 5
1.5t_CLCL – 5
t_CLCL – 5
2.0t_CLCL – 5
VARIABLE
CLOCK MAX.
UNITS
nS
nS
nS
nS
2.0t_CLCL – 20
nS
t_MCS – 20
nS
t_CLCL – 5
nS
2.0t_CLCL – 5
2.5t_CLCL – 5
nS
t_MCS + 2t_CLCL – 40
3.0t_CLCL – 20
nS
2.0t_CLCL – 5
0.5t_CLCL + 5
nS
1.5t_CLCL + 5
nS
STRECH
t_MCS = 0
t_MCS>0
t_MCS = 0
t_MCS>0
t_MCS = 0
t_MCS>0
t_MCS = 0
t_MCS>0
t_MCS = 0
t_MCS>0
t_MCS = 0
t_MCS>0
t_MCS = 0
t_MCS>0
t_MCS = 0
t_MCS>0
t_MCS = 0
t_MCS>0
Port 2 Address to RD or WR
Low
t_AVWL2
1.5t_CLCL – 5
2.5t_CLCL – 5
nS
t_MCS = 0
t_MCS>0
Data Valid to WR Transition
Data Hold after Write
t_QVWX
t_WHQX
-5
1.0t_CLCL – 5
t_CLCL – 5
2.0t_CLCL – 5
nS
t_MCS = 0
t_MCS>0
nS
t_MCS = 0
t_MCS>0
RD Low to Address Float
t_RLAZ
0.5t_CLCL – 5
nS
RD or WR high to ALE high
t_WHLH
0
1.0t_CLCL – 5
10
1.0t_CLCL + 5
nS
t_MCS = 0
t_MCS>0
Note: tMCS is a time period related to the Stretch memory cycle selection. The following table shows the time period of tMCS
for each selection of the Stretch value.
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Publication Release Date: June 30, 2009
Revision A10