W77E532 Datasheet, PDF (22/86 Pages) Winbond – 8 BIT MICROCONTROLLER

W77E532/W77E532A
ISP Address High Byte
Bit:
7
6
5
4
3
2
1
0
A15 A14 A13 A12 A11 A10
A9
A8
Mnemonic: SFRAH
Address: Adh
High byte destination address for In System Programming operations. SFRAH and SFRAL address a
specific ROM bytes for erasure, escription or read.
ISP Data Buffer
Bit:
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Mnemonic: SFRFD
Address: Aeh
In ISP mode, read/write a specific byte ROM content must go through SFRFD register.
ISP Operation Modes
Bit:
7
6
5
BANK WFWIN NOE
4
3
2
1
0
NCE CTRL3 CTRL2 CTRL1 CTRL0
Mnemonic: SFRCN
Address: Afh
BANK: Select APFLASH banks for ISP. Set it 1 access to APFLASH1, clear it to APFLASH0.
WFWIN: Destenation ROM bank for programming, erasure and read. 0 = APFLASHx, 1 = LDFLASH.
NOE: Flash EPROM output enable.
NCE: Flash EPROM chip enable.
CTRL[3:0]: Mode Selection.
ISP MODE
BANK WFWIN NOE
Erase 4KB LDFLASH
0
1
1
Erase 64K APFLASH0
0
0
1
Erase 64K APFLASH1
1
0
1
Program 4KB LDFLASH
0
1
1
Program 64KB APFLASH0
0
0
1
Program 64KB APFLASH1
1
0
1
Read 4KB LDFLASH
0
1
0
Read 64KB APFLASH0
0
0
0
Read 64KB APFLASH1
1
0
0
NCE CTRL<3:0>
0
0010
0
0010
0
0010
0
0001
0
0001
0
0001
0
0000
0
0000
0
0000
SFRAH,
SFRAL
X
X
X
Address in
Address in
Address in
Address in
Address in
Address in
SFRFD
X
X
X
Data in
Data in
Data in
Data out
Data out
Data out
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Publication Release Date: June 30, 2009
Revision A10