W77E532 Datasheet, PDF (24/86 Pages) Winbond – 8 BIT MICROCONTROLLER

W77E532/W77E532A
Slave Address Mask Enable 1
Bit:
7
6
5
4
3
2
1
0
Mnemonic: SADEN1
Address: Bah
SADEN1:This register enables the Automatic Address Recognition feature of the Serial port 1. When
a bit in the SADEN1 is set to 1, the same bit location in SADDR1 will be compared with the
incoming serial data. When SADEN1.n is 0, then the bit becomes a “don’t care” in the
comparison. This register enables the Automatic Address Recognition feature of the Serial
port 1. When all the bits of SADEN1 are 0, interrupt will occur for any incoming address.
Serial Port Control 1
Bit:
7
SM0_1/FE_1
6
SM1_1
5
SM2_1
4
REN_1
3
TB8_1
2
RB8_1
1
TI_1
0
RI_1
Mnemonic: SCON1
Address: C0h
SM0_1/FE_1: Serial port 1, Mode 0 bit or Framing Error Flag 1: The SMOD0 bit in PCON SFR
determines whether this bit acts as SM0_1 or as FE_1. the operation of SM0_1 is
described below. When used as FE_1, this bit will be set to indicate an invalid stop bit.
This bit must be manually cleared in software to clear the FE_1 condition.
SM1_1:
Serial port 1 Mode bit 1:
SM0_1 SM1_1
00
01
10
11
Mode
0
1
2
3
Description
Synchronous
Asynchronous
Asynchronous
Asynchronous
Length
8
10
11
11
Baud rate
4/12 Tclk
variable
64/32 Tclk
variable
SM2_1: Multiple processors communication. Setting this bit to 1 enables the multiprocessor
communication feature in mode 2 and 3. In mode 2 or 3, if SM2_1 is set to 1, then RI_1 will
not be activated if the received 9^th data bit (RB8_1) is 0. In mode 1, if SM2_1 = 1, then RI_1
will not be activated if a valid stop bit was not received. In mode 0, the SM2_1 bit controls the
serial port 1 clock. If set to 0, then the serial port 1 runs at a divide by 12 clock of the
oscillator. This gives compatibility with the standard 8052. When set to 1, the serial clock
become divide by 4 of the oscillator clock. This results in faster synchronous serial
communication.
REN_1:
disabled.
Receive enable: When set to 1 serial reception is enabled, otherwise reception is
TB8_1: This is the 9^th bit to be transmitted in modes 2 and 3. This bit is set and cleared by software
as desired.
RB8_1: In modes 2 and 3 this is the received 9^th data bit. In mode 1, if SM2_1 = 0, RB8_1 is the stop
bit that was received. In mode 0 it has no function.
TI_1: Transmit interrupt flag: This flag is set by hardware at the end of the 8^th bit time in mode 0, or
at the beginning of the stop bit in all other modes during serial transmission. This bit must be
cleared by software.
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Publication Release Date: June 30, 2009
Revision A10