W77E532 Datasheet, PDF (61/86 Pages) Winbond – 8 BIT MICROCONTROLLER

W77E532/W77E532A
Mode 2
This mode uses a total of 11 bits in asynchronous full-duplex communication. The functional
description is shown in the figure below. The frame consists of one start bit (0), 8 data bits (LSB first), a
programmable 9^th bit (TB8) and a stop bit (0). The 9^th bit received is put into RB8. The baud rate is
programmable to 1/32 or 1/64 of the oscillator frequency, which is determined by the SMOD bit in
PCON SFR. Transmission begins with a write to SBUF. The serial data is brought out on to TxD pin at
C1 following the first roll-over of the divide by 16 counter. The next bit is placed on TxD pin at C1
following the next rollover of the divide by 16 counter. Thus the transmission is synchronized to the
divide by 16 counter, and not directly to the write to SBUF signal. After all 9 bits of data are transmitted,
the stop bit is transmitted. The TI flag is set in the C1 state after the stop bit has been put out on TxD
pin. This will be at the 11^th rollover of the divide by 16 counter after a write to SBUF. Reception is
enabled only if REN is high. The serial port actually starts the receiving of serial data, with the detection
of a falling edge on the RxD pin. The 1-to-0 detector continuously monitors the RxD line, sampling it at
the rate of 16 times the selected baud rate. When a falling edge is detected, the divide by 16 counter is
immediately reset. This helps to align the bit boundaries with the rollovers of the divide by 16 counter.
The 16 states of the counter effectively divide the bit time into 16 slices. The bit detection is done on a
best of three basis. The bit detector samples the RxD pin, at the 8^th, 9^th and 10^th counter states. By
using a majority 2 of 3 voting system, the bit value is selected. This is done to improve the noise
rejection feature of the serial port.
Clock Source
Mode input
div. by 4 osc/2
div. by 64 osc/32
div. by 1024 osc/512
2
Write to
SBUF
TB8
Internal
Data Bus
SMOD= _{0 1}
(SMOD_1)
16
16
SAMPLE
1-TO-0
DETECTOR
TX START
TX CLOCK
TX
SHIFT
TI
SERIAL
CONTROLLER _RI
RX CLOCK
RX START
LOAD
SBUF
RX SHIFT
RXD
BIT
DETECTOR
D8
STOP
PARIN
START
LOAD
SOUT
CLOCK
Transmit Shift Register
TXD
Serial Port
Interrupt
CLOCK
PAROUT
SBUF
SIN
D8
RB8
Receive Shift Register
Read
SBUF
Internal
Data
Bus
Figure 22. Serial Port Mode 2
If the first bit detected after the falling edge of RxD pin, is not 0, then this indicates an invalid start bit,
and the reception is immediately aborted. The serial port again looks for a falling edge in the RxD line.
If a valid start bit is detected, then the rest of the bits are also detected and shifted into the SBUF. After
shifting in 9 data bits, there is one more shift to do, after which the SBUF and RB8 are loaded and RI is
set. However certain conditions must be met before the loading and setting of RI can be done.
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Publication Release Date: June 30, 2009
Revision A10