W77E532 Datasheet, PDF (55/86 Pages) Winbond – 8 BIT MICROCONTROLLER

W77E532/W77E532A
Programmable Clock-out
Timer 2 is equipped with a new clock-out feature which outputs a 50% duty cycle clock on P1.0. It can
be invoked as a programmable clock generator. To configure Timer 2 with clock-out mode, software
must initiate it by setting bit T2OE = 1, C/T2 = 0 and CP/RL = 0. Setting bit TR2 will start the timer. This
mode is similar to the baud rate generator mode, it will not generate an interrupt while Timer 2
overflow. So it is possible to use Timer 2 as a baud rate generator and a clock generator at the same
time. The clock-out frequency is determined by the following equation:
The Clock-Out Frequency = Oscillator Frequency / [4 x (65536-RCAP2H, RCAP2L)]
Clock Source
Mode input
div. by 4
osc/2
div. by 64 osc/32
div. by 1024 osc/512
TL2 TH2
1/2
T2=P1.0
TR2 = T2CON.2
T2EX = P1.1
EXEN2 = T2CON.3
RCAP2L RCAP2H
EXF2
T2CON.6
Timer 2
Interrupt
Figure 18. Programmable Clock-Out Mode
Watchdog Timer
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the
system clock. The divider output is selectable and determines the time-out interval. When the time-out
occurs a flag is set, which can cause an interrupt if enabled, and a system reset can also be caused if it
is enabled. The interrupt will occur if the individual interrupt enable and the global enable are set. The
interrupt and reset functions are independent of each other and may be used separately or together
depending on the users software.
0
Clock Source
Mode input
div. by 4
osc/1
div. by 64 osc/16
div. by 1024 osc/256
Reset Watchdog
RWT (WDCON.0)
16
17 19
20 22
23 25
WD1,WD0
00
01
10 _Time-out
11
WDIF
EWDI(EIE.4)
WTRF
512 clock
delay
Enable Watchdog timer reset
EWT(WDCON.1)
Figure 19. Watchdog Timer
Interrupt
Reset
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Publication Release Date: June 30, 2009
Revision A10