W77E532 Datasheet, PDF (56/86 Pages) Winbond – 8 BIT MICROCONTROLLER

W77E532/W77E532A
The Watchdog timer should first be restarted by using RWT. This ensures that the timer starts from a
known state. The RWT bit is used to restart the watchdog timer. This bit is self clearing, i.e. after writing
a 1 to this bit the software will automatically clear it. The watchdog timer will now count clock cycles.
The time-out interval is selected by the two bits WD1 and WD0 (CKCON.7 and CKCON.6). When the
selected time-out occurs, the Watchdog interrupt flag WDIF (WDCON.3) is set. After the time-out has
occurred, the watchdog timer waits for an additional 512 clock cycles. If the Watchdog Reset EWT
(WDCON.1) is enabled, then 512 clocks after the time-out, if there is no RWT, a system reset due to
Watchdog timer will occur. This will last for two machine cycles, and the Watchdog timer reset flag
WTRF (WDCON.2) will be set. This indicates to the software that the watchdog was the cause of the
reset.
When used as a simple timer, the reset and interrupt functions are disabled. The timer will set the
WDIF flag each time the timer completes the selected time interval. The WDIF flag is polled to detect a
time-out and the RWT allows software to restart the timer. The Watchdog timer can also be used as a
very long timer. The interrupt feature is enabled in this case. Every time the time-out occurs an interrupt
will occur if the global interrupt enable EA is set.
The main use of the Watchdog timer is as a system monitor. This is important in real-time control
applications. In case of some power glitches or electro-magnetic interference, the processor may begin
to execute errant code. If this is left unchecked the entire system may crash. Using the watchdog timer
interrupt during software development will allow the user to select ideal watchdog reset locations. The
code is first written without the watchdog interrupt or reset. Then the watchdog interrupt is enabled to
identify code locations where interrupt occurs. The user can now insert instructions to reset the
watchdog timer which will allow the code to run without any watchdog timer interrupts. Now the
watchdog timer reset is enabled and the watchdog interrupt may be disabled. If any errant code is
executed now, then the reset watchdog timer instructions will not be executed at the required instants
and watchdog reset will occur.
The watchdog time-out selection will result in different time-out values depending on the clock speed.
The reset, when enabled, will occur 512 clocks after the time-out has occurred.
Table 9. Time-out values for the Watchdog timer
WD1
0
0
1
1
WD0
0
1
0
1
WATCHDOG
INTERVAL
2¹⁷
2²⁰
2²³
2²⁶
NUMBER OF
CLOCKS
131072
1048576
8388608
67108864
TIME
@ 1.8432 MHZ
71.11 mS
568.89 mS
4551.11 mS
36408.88 mS
TIME
@ 10 MHZ
13.11 mS
104.86 mS
838.86 mS
6710.89 mS
TIME
@ 25 MHZ
5.24 mS
41.94 mS
335.54 mS
2684.35 mS
The Watchdog timer will de disabled by a power-on/fail reset. The Watchdog timer reset does not
disable the watchdog timer, but will restart it. In general, software should restart the timer to put it into a
known state.
The control bits that support the Watchdog timer are discussed below.
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Publication Release Date: June 30, 2009
Revision A10