W77E532 Datasheet, PDF (25/86 Pages) Winbond – 8 BIT MICROCONTROLLER

W77E532/W77E532A
RI_1: Receive interrupt flag: This flag is set by hardware at the end of the 8^th bit time in mode 0, or
halfway through the stop bits time in the other modes during serial reception. However the
restrictions of SM2_1 apply to this bit. This bit can be cleared only by software.
Serial Data Buffer 1
Bit:
7
6
5
4
3
2
1
0
SBUF1.7 SBUF1.6 SBUF1.5 SBUF1.4 SBUF1.3 SBUF1.2 SBUF1.1 SBUF1.0
Mnemonic: SBUF1
Address: C1h
SBUF1.7-0: Serial data of the serial port 1 is read from or written to this location. It actually consists of
two separate 8-bit registers. One is the receive resister, and the other is the transmit
buffer. Any read access gets data from the receive data buffer, while write accesses are
to the transmit data buffer.
WSCON
Bit:
7
6
5
4
3
2
1
0
WS
-
-
-
-
-
-
-
Mnemonic: WSCON
Address: C2h
WS: Wait State Signal Enable. Setting this bit enables the WAIT signal on P4.0. The device will
sample the wait state control signal WAIT via P4.0 during MOVX instruction. This bit is time
access protected.
TA REG C7H
WSCON REG C2H
CKCON REG 8EH
MOV
TA, #AAH
MOV
TA, #55H
ORL
WSCON, #10000000B ; Set WS bit and stretch value = 0 to enable wait
signal.
Power Management Register
Bit:
7
6
5
4
CD1
CD0 SWB
-
3
2
1
-
ALE-OFF
-
0
DME0
Mnemonic: PMR
Address: C4h
CD1, CD0: Clock Divide Control. These bit selects the number of clocks required to generate one
machine cycle. There are three modes including divide by 4, 64 or 1024. Switching
between modes must first go back divide by 4 mode. For instance, to go from 64 to 1024
clocks/machine cycle the device must first go from 64 to 4 clocks/machine cycle, and then
from 4 to 1024 clocks/machine cycle.
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Publication Release Date: June 30, 2009
Revision A10