W77E532 Datasheet, PDF (11/86 Pages) Winbond – 8 BIT MICROCONTROLLER

W77E532/W77E532A
A brief description of the SFRs now follows.
Port 0
Bit:
7
6
5
4
3
2
1
0
P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
Mnemonic: P0
Address: 80h
Port 0 is an open-drain bi-directional I/O port. This port also provides a multiplexed low order
address/data bus during accesses to external memory. Besides, it has internal pull-up resisters
enabled by setting P0UP of P4CSIN (A2H) to high.
Stack Pointer
Bit:
7
SP.7
6
SP.6
5
SP.5
4
SP.4
3
SP.3
2
SP.2
1
SP.1
0
SP.0
Mnemonic: SP
Address: 81h
The Stack Pointer stores the Scratchpad RAM address where the stack begins. In other words, it
always points to the top of the stack.
Data Pointer Low
Bit:
7
6
5
4
3
2
1
0
DPL.7 DPL.6 DPL.5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0
Mnemonic: DPL
This is the low byte of the standard 8052 16-bit data pointer.
Address: 82h
Data Pointer High
Bit:
7
6
5
4
3
2
1
0
DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0
Mnemonic: DPH
Address: 83h
This is the high byte of the standard 8052 16-bit data pointer.
Data Pointer Low1
Bit:
7
6
5
4
3
2
1
0
DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0
Mnemonic: DPL1
Address: 84h
This is the low byte of the new additional 16-bit data pointer that has been added to the W77E532A.
The user can switch between DPL, DPH and DPL1, DPH1 simply by setting register DPS = 1. The
instructions that use DPTR will now access DPL1 and DPH1 in place of DPL and DPH. If they are not
required they can be used as conventional register locations by the user.
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Publication Release Date: June 30, 2009
Revision A10