W77E532 Datasheet, PDF (26/86 Pages) Winbond – 8 BIT MICROCONTROLLER

W77E532/W77E532A
CD1, CD0
0
0
0
1
1
0
1
1
CLOCKS/MACHINE CYCLE
Reserved
4
64
1024
SWB:
Switchback Enable. Setting this bit allows an enabled external interrupt or serial port activity
to force the CD1, CD0 to divide by 4 state (0, 1). The device will switch modes at the start of
the jump to interrupt service routine while a external interrupt is enabled and actually
recongnized by microcontroller. While a serial port reception, the switchback occurs at the
start of the instruction following the falling edge of the start bit.
ALE0FF: This bit disables the expression of the ALE signal on the device pin during all on-board
program and data memory accesses. External memory accesses will automatically enable
ALE independent of ALEOFF.
0 = ALE expression is enable; 1 = ALE expression is disable
DME0: This bit determines the on-chip MOVX SRAM to be enabled or disabled. Set this bit to 1 will
enable the on-chip 1KB MOVX SRAM.
Status Register
Bit:
7
-
6
5
4
3
2
1
0
HIP
LIP XTUP SPTA1 SPRA1 SPTA0 SPRA0
Mnemonic: STATUS
Address: C5h
HIP: High Priority Interrupt Status. When set, it indicates that software is servicing a high priority
interrupt. This bit will be cleared when the program executes the corresponding RETI
instruction.
LIP: Low Priority Interrupt Status. When set, it indicates that software is servicing a low priority
interrupt. This bit will be cleared when the program executes the corresponding RETI
instruction.
XTUP: Crystal Oscillator Warm-up Status. When set, this bit indicates CPU has detected clock to be
ready. Each time the crystal oscillator is restarted by exit from power down mode, hardware will
clear this bit. This bit is set to 1 after a power-on reset.
SPTA1: Serial Port 1 Transmit Activity. This bit is set during serial port 1 is currently transmitting data.
It is cleared when TI_1 bit is set by hardware. Changing the Clock Divide Control bits
CD0, CD1 will be ignored when this bit is set to 1 and SWB = 1.
SPRA1: Serial Port 1 Receive Activity. This bit is set during serial port 1 is currently receiving a data. It
is cleared when RI_1 bit is set by hardware. Changing the Clock Divide Control bits CD0, CD1
will be ignored when this bit is set to 1 and SWB = 1.
SPTA0: Serial Port 0 Transmit Activity. This bit is set during serial port 0 is currently transmitting data.
It is cleared when TI bit is set by hardware. Changing the Clock Divide Control bits CD0, CD1
will be ignored when this bit is set to 1 and SWB = 1.
SPRA0: Serial Port 0 Receive Activity. This bit is set during serial port 0 is currently receiving a data. It
is cleared when RI bit is set by hardware. Changing the Clock Divide Control bits CD0, CD1
will be ignored when this bit is set to 1 and SWB = 1.
Timed Access
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Publication Release Date: June 30, 2009
Revision A10