KX022-1020 Datasheet, PDF (50/75 Pages) List of Unclassifed Manufacturers – Accelerometer Specifications

± 2g / 4g / 8g Tri-axis Digital
Accelerometer Specifications
PART NUMBER:
KX022-1020
Rev. 11.0
10-Sep-15
R/W
STD7
Bit7
R/W
STD6
Bit6
R/W
STD5
Bit5
R/W
STD4
Bit4
R/W
STD3
Bit3
R/W
R/W
R/W
STD2
STD1
STD0
Bit2
Bit1
Bit0
I²C Address: 0x29h
Reset Value
00100100
TLT
This register contains counter information for the detection of a tap event. When the Directional Tap^TM
ODR is 400Hz or less, every count is calculated as 1/ODR delay period. When the Directional Tap^TM
ODR is 800Hz, every count is calculated as 2/ODR delay period. When the Directional Tap^TM ODR is
1600Hz, every count is calculated as 4/ODR delay period. The Directional Tap^TM ODR is user-defined
per Table 19. In order to ensure that only tap events are detected, this time limit is used. This register
sets the total amount of time that the tap algorithm will count samples that are above the PI threshold
(TTL) during a potential tap event. It is used during both single and double tap events. However,
reporting of single taps on the physical interrupt pin INT1 or INT2 will occur at the end of the TWS. The
Kionix recommended default value for TLT is 0.1 seconds (0x28h). Note that to properly change the
value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”.
R/W
TLT7
Bit7
R/W
TLT6
Bit6
R/W
TLT5
Bit5
R/W
TLT4
Bit4
R/W
TLT3
Bit3
R/W
TLT2
Bit2
R/W
R/W
TLT1
TLT0
Bit1
Bit0
I²C Address: 0x2Ah
Reset Value
00101000
TWS
This register contains counter information for the detection of single and double taps. When the
Directional Tap^TM ODR is 400Hz or less, every count is calculated as 1/ODR delay period. When the
Directional Tap^TM ODR is 800Hz, every count is calculated as 2/ODR delay period. When the
Directional Tap^TM ODR is 1600Hz, every count is calculated as 4/ODR delay period. The Directional
Tap^TM ODR is user-defined per Table 19. It defines the time window for the entire tap event, single or
double, to occur. Reporting of single taps on the physical interrupt pin INT1 or INT2 will occur at the
end of this tap window. The Kionix recommended default value for TWS is 0.4 seconds (0xA0h). Note
that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”.
R/W
TWS7
Bit7
R/W
TWS6
Bit6
R/W
TWS5
Bit5
R/W
TWS4
Bit4
R/W
TWS3
Bit3
R/W
R/W
R/W
TWS2 TWS1 TWS0
Bit2
Bit1
Bit0
I²C Address: 0x2Bh
Reset Value
10100000
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