KX022-1020 Datasheet, PDF (20/75 Pages) List of Unclassifed Manufacturers – Accelerometer Specifications

± 2g / 4g / 8g Tri-axis Digital
Accelerometer Specifications
PART NUMBER:
KX022-1020
Rev. 11.0
10-Sep-15
It is mandatory that receiving devices acknowledge (ACK) each transaction. Therefore, the transmitter must
release the SDA line during this ACK pulse. The receiver then pulls the data line low so that it remains stable
low during the high period of the ACK clock pulse. A receiver that has been addressed, whether it is Master or
Slave, is obliged to generate an ACK after each byte of data has been received. To conclude a transaction,
the Master must transmit a stop condition (P) by transitioning the SDA line from low to high while SCL is high.
The I²C bus is now free. Note that if the KX022 is accessed through I²C protocol before the startup is finished
a NACK signal is sent.
Writing to 8-bit Register
Upon power up, the Master must write to the KX022’s control registers to set its operational mode. Therefore,
when writing to a control register on the I²C bus, as shown Sequence 1 on the following page, the following
protocol must be observed: After a start condition, SAD+W transmission, and the KX022 ACK has been
returned, an 8-bit Register Address (RA) command is transmitted by the Master. This command is telling the
KX022 to which 8-bit register the Master will be writing the data. Since this is I²C mode, the MSB of the RA
command should always be zero (0). The KX022 acknowledges the RA and the Master transmits the data to
be stored in the 8-bit register. The KX022 acknowledges that it has received the data and the Master
transmits a stop condition (P) to end the data transfer. The data sent to the KX022 is now stored in the
appropriate register. The KX022 automatically increments the received RA commands and, therefore, multiple
bytes of data can be written to sequential registers after each Slave ACK as shown in Sequence 2 on the
following page.
Note** If a STOP condition is sent on the least significant bit of write data or the following master acknowledge
cycle, the last write operation is not guaranteed and it may alter the content of the affected registers.
Reading from 8-bit Register
When reading data from a KX022 8-bit register on the I²C bus, as shown in Sequence 3 on the next page, the
following protocol must be observed: The Master first transmits a start condition (S) and the appropriate Slave
Address (SAD) with the LSB set at ‘0’ to write. The KX022 acknowledges and the Master transmits the 8-bit
RA of the register it wants to read. The KX022 again acknowledges, and the Master transmits a repeated start
condition (Sr). After the repeated start condition, the Master addresses the KX022 with a ‘1’ in the LSB
(SAD+R) to read from the previously selected register. The Slave then acknowledges and transmits the data
from the requested register. The Master does not acknowledge (NACK) it received the transmitted data, but
transmits a stop condition to end the data transfer. Note that the KX022 automatically increments through its
sequential registers, allowing data to be read from multiple registers following a single SAD+R command as
shown below in Sequence 4 on the following page. Reading data from a buffer read register is a special case
because if register address (RA) is set to buffer read register (BUF_READ) in Sequence 4, the register auto-
increment feature is automatically disabled. Instead, the Read Pointer will increment to the next data in the
buffer, thus allowing reading multiple bytes of data from the buffer using a single SAD+R command.
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