KX022-1020 Datasheet, PDF (49/75 Pages) List of Unclassifed Manufacturers – Accelerometer Specifications

± 2g / 4g / 8g Tri-axis Digital
Accelerometer Specifications
PART NUMBER:
KX022-1020
Rev. 11.0
10-Sep-15
TTL
This register represents the 8-bit (0d– 255d) jerk low threshold to determine if a tap is detected. The
Performance Index (PI) is the jerk signal that is expected to be greater than this threshold and less
than the TTH threshold during single and double tap events. The Kionix recommended default value is
26 (0x1Ah). Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must
first be set to “0”.
R/W
TTL7
Bit7
R/W
TTL6
Bit6
R/W
TTL5
Bit5
R/W
TTL4
Bit4
R/W
TTL3
Bit3
R/W
TTL2
Bit2
R/W
R/W
TTL1
TTL0
Bit1
Bit0
I²C Address: 0x27h
Reset Value
00011010
FTD
This register contains counter information for the detection of any tap event. When the Directional
TapTM ODR is 400Hz or less, every count is calculated as 1/ODR delay period. When the Directional
TapTM ODR is 800Hz, every count is calculated as 2/ODR delay period. When the Directional TapTM
ODR is 1600Hz, every count is calculated as 4/ODR delay period. The Directional TapTM ODR is
user-defined per Table 19. In order to ensure that only tap events are detected, these time limits are
used. A tap event must be above the performance index threshold for at least the low limit (FTDL0 –
FTDL2) and no more than the high limit (FTDH0 – FTDH4). The Kionix recommended default value for
the high limit is 0.05 seconds and for the low limit is 0.005 seconds (0xA2h). Note that to properly
change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”.
R/W
FTDH4
Bit7
R/W
FTDH3
Bit6
R/W
FTDH2
Bit5
R/W
FTDH1
Bit4
R/W
FTDH0
Bit3
R/W
R/W
R/W
FTDL2 FTDL1 FTDL0
Bit2
Bit1
Bit0
I²C Address: 0x28h
Reset Value
10100010
STD
This register contains counter information for the detection of a double tap event. When the Directional
Tap^TM ODR is 400Hz or less, every count is calculated as 1/ODR delay period. When the Directional
Tap^TM ODR is 800Hz, every count is calculated as 2/ODR delay period. When the Directional Tap^TM
ODR is 1600Hz, every count is calculated as 4/ODR delay period. The Directional Tap^TM ODR is user-
defined per Table 19. In order to ensure that only tap events are detected, this time limit is used. This
register sets the total amount of time that the two taps in a double tap event can be above the PI
threshold (TTL). The Kionix recommended default value for STD is 0.09 seconds (0x24h). Note that to
properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”.
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