KX022-1020 Datasheet, PDF (47/75 Pages) List of Unclassifed Manufacturers – Accelerometer Specifications

± 2g / 4g / 8g Tri-axis Digital
Accelerometer Specifications
PART NUMBER:
KX022-1020
Rev. 11.0
10-Sep-15
TILT_TIMER
This register is the initial count register for the tilt position state timer (0 to 255 counts). Every count is
calculated as 1/ODR delay period, where the ODR is user-defined per Table 18. A new state must be
valid as many measurement periods before the change is accepted. Note that to properly change the
value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”.
R/W
TSC7
Bit7
R/W
TSC6
Bit6
R/W
TSC5
Bit5
R/W
TSC4
Bit4
R/W
TSC3
Bit3
R/W
R/W
R/W
TSC2
TSC1
TSC0
Bit2
Bit1
Bit0
I²C Address: 0x22h
Reset Value
00000000
WUFC
This register is the initial count register for the motion detection timer (0 to 255 counts). Every count is
calculated as 1/ODR delay period, where the ODR is user-defined per Table 20. A new state must be
valid as many measurement periods before the change is accepted. Note that to properly change the
value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”.
R/W
WUFC7
Bit7
R/W
WUFC6
Bit6
R/W
WUFC5
Bit5
R/W
WUFC4
Bit4
R/W
WUFC3
Bit3
R/W
R/W
R/W
WUFC2 WUFC1 WUFC0
Bit2
Bit1
Bit0
I²C Address: 0x23h
Reset Value
00000000
TDTRC
This register is responsible for enabling/disabling reporting of Tap/Double Tap. Note that to properly
change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
DTRE STRE
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
00000011
I²C Address: 0x24h
DTRE enables/disables the double tap interrupt
DTRE = 0 – do not update/trigger interrupts on double tap events
DTRE = 1 –update interrupts on double tap events
STRE enables/disables single tap interrupt
STRE = 0 – do not update/trigger interrupts on single tap events
STRE = 1 –update interrupts on single tap events
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