KX022-1020 Datasheet, PDF (29/75 Pages) List of Unclassifed Manufacturers – Accelerometer Specifications

± 2g / 4g / 8g Tri-axis Digital
Accelerometer Specifications
PART NUMBER:
KX022-1020
Rev. 11.0
10-Sep-15
3-Wire Read and Write Registers
The registers embedded in the KX022 have 8-bit addresses. Upon power up, the Master must write to the
accelerometer’s control registers to set its operational mode. On the falling edge of nCS, a 2-byte command is
written to the appropriate control register. The first byte initiates the write to the appropriate register, and is
followed by the user-defined, data byte. The MSB (Most Significant Bit) of the register address byte will
indicate “0” when writing to the register and “1” when reading from the register. A read operation occurs over
17 clock cycles and a write operation occurs over 16 clock cycles. All commands are sent MSB first. The host
must return nCS high for at least one clock cycle before the next data request. However, when data is being
read from a buffer read register (BUF_READ), the nCS signal can remain low until the buffer is read. Figure 6
below shows the timing diagram for carrying out an 8-bit register write operation.
SCLK
SDI
CS
A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
(MSB)
(MSB)
Figure 6: Timing Diagram for 8-Bit Register Write Operation
In order to read an 8-bit register, an 8-bit register address must be written to the accelerometer to initiate the
read. The MSB of this register address byte will indicate “0” when writing to the register and “1” when reading
from the register. Upon receiving the address, the accelerometer returns the 8-bit data stored in the
addressed register. For 3-wire read operations, one extra clock cycle between the address byte and the data
output byte is required. Therefore, this operation occurs over 17 clock cycles. All returned data is sent MSB
first, and the host must return nCS high for at least one clock cycle before the next data request. Figure 7
shows the timing diagram for an 8-bit register read operation.
SCLK
SDI
CS
A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ^HI-Z
(MSB)
(MSB)
Figure 7: Timing Diagram for 8-Bit Register Read Operation
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