ACD82224 Datasheet, PDF (9/77 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch

5. FUNCTIONAL DESCRIPTION
The MAC controller performs transmitting, receiving, and deferring functions, in accordance to
the 802.3 and 802.3u specification. The MAC logic also handles frame detection, frame
generation, error detection, error handling, status indication and flow control functions. Under
full-duplex mode, the flow control is implemented in compliance with IEEE 802.3x standard.
Frame Format
The ACD82224 assumes that the received data packet will have the following format:
Preamble
SFD
DA
SA
Type/Len
Data
FCS
Where,
• Preamble is a repetitive pattern of ‘1010….’ of any length with nibble alignment.
• SFD (Start Frame Delimiter) is defined as an octet pattern of 10101011.
• DA (Destination Address) is a 48-bit field that specifies the MAC address of the destined
DTE. For any frame with “1” in the first bit of the DA, with the exception of the BPDU address
(the reserved group address described in table 3-5 of IEEE 802.1d), the ACD82224 will treat
it as a broadcast/multicast frame. It will forward the frame to all ports within the source port’s
VLAN, except the source port itself.
• SA (Source Address) is a 48-bit field that contains the MAC address of the source DTE that
is transmitting the frame to the ACD82224. After a frame is received with no error, the SA is
learned as the port’s MAC address.
• Type/Len field is a 2-byte field that specifies the type (DIX Ethernet frame) or length (IEEE
802.3 frame) of the frame. The ACD82224 does not process this information, unless it is a
Pause-Frame
• Data is the encapsulated information within the Ethernet Packet. The ACD82224 does not
process any of the data information in this field.
• FCS (Frame Check Sequence) is a 32-bit field of CRC (Cyclic Redundancy Check) value
based on the destination address, the source address, the type/length and the data field. The
ACD82224 will verify the FCS field for each frame. The procedure for computing FCS is
described in the section “FCS Calculation.”
Start of Frame Detection
When a port’s MAC logic detects the assertion of the CRS_DV signal in the RMII interface, it will
start a receiving process. The received data will come through a 2-bit wide data bus, clocked by
the 50 MHz receiving-clock from the ACD82224. It will then pass a frame alignment circuit,
which will convert the 2-bit signal into a single bit stream and detect the occurrence of the SFD
pattern (10101011). All signals before the SFD are filtered out and the rest of the data frame will
be stored into the frame buffer of the switch.
Frame Reception
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