ACD82224 Datasheet, PDF (24/77 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch

Table-6.9: ARL & MIB Interfaces Signals
Name
Type
ARL Interface
MIB Interface
DATA[47:0] O Frame Data
BE[2:0]
O Byte Enable: BE[0:2]
EOF
O End of Frame: EOF
SWDIR[1:0] O Data Direction Indicator :
00 = idle, 01 = receive, 10 = transmit, 11 = control
SWSYNC
O Port synchronization: indicating when Port-0 is driving DAT[0:47]
SWSTAT[3:0] O
SWRXCLK
O
Data state indicator:
0000 – Idle
0001 – First word (DA)
0010 – Second word (SA)
0011 – Third through last word
0100 – Filter Event
0101 – Drop Event
0110 – Jabber
0111 – False Carrier (receive)
- Deferred Transmission (transmit)
1000 – Alignment error (receive)
- Single Collision (transmit)
1001 – Flow Control (receive)
- Multiple Collision (transmit)
1010 – Short Event (receive)
- Excessive Collision (transmit)
1011 – Runt (receive)
- Late Collision (transmit)
1100 – Symbol Error
1101 – FCS Error
1110 – Long Event
1111 – Reserved
Receive Clock
SWTXCLK
O
NA
Transmit Clock
P-23 MII
NA
The default CPU port, share
with regular Port-23 traffic
ARLDI[3:0]
I
ARL Data Input:
NA
Returns 12-bit (3-cycles) ARL look-up result to
the switch:
•Bit[11:7] - Source Port ID (0 - 23)
•Bit[6:5] – Look-up Result:
00 – reserved
01 – matched
10 – not matched
11 – forced discard
•Bit[4:0] - Destination Port ID (0 - 23)
ARLDIV
I ARL Data Input Valid: Assertion to indicate start
NA
of a new result on ARLDI[0:3]
LED Interface
The status of each port is displayed on the LED interface for every 50ms. LEDVLD0 and
LEDVLD1 are used to indicate the start and end of the LED data. LED data is clocked out by the
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