ACD82224 Datasheet, PDF (38/77 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch

PAUSE register (register 26)
The PAUSE register defines the pause-frame based flow control capability of each port. Table-
7.26 describes all the bits of this register.
Table-7.26: PAUSE Register
Bit
Description
[0:23]
0 – Port X Pause-Frame disabled
1 – Port X Pause-Frame enabled
Default
0
DPLX register (register 27)
The DPLX register specifies or indicates the half/full-duplex mode of each port. Table-7.27
describes all the bits of this register.
Table-7.27: DPLX Register
Bit
Description
[0:23]
0 – Port X under half duplex mode
1 – Port X under full duplex mode
Default
0
nPM register (register 29)
The nPM register indicates the automatic PHY management capability of each port. If a bit is set
in this register, the corresponding SPEED, LINK, DPLX, and PAUSE registers of the port will not
be updated by Automatic PHY Management. Table-7.29 describes all the bits of this register.
Table-7.29: nPM Register
Bit
Description
[0:23]
0 – Port X’s status update enabled
1 – Port X’s status update disabled
Default
0
ERRMSK register (register 30)
The ERRMSK register defines certain errors as system errors. It is reserved for factory use only.
Table-7.30 lists all the error masks specified by this register.
Table-7.30: ERRMSK register
Bit
Description
0
Reserved
1
Reserved
2
Reserved
3
Reserved
4
Reserved
5
Reserved
6
Reserved
7
Reserved
Default
1
1
1
1
1
1
1
1
Shared Pin
P00TXD0
P00TXD1
P02TXD0
P02TXD1
P03TXD0
P03TXD1
P05TXD0
P05TXD1
CLKADJ register (register 31)
The CLKADJ register defines the delay time of the ARLCLK relative to the transition edge of the
data signals. The ARLCLK provides reference timing for supporting chips, such as the
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