ACD82224 Datasheet, PDF (29/77 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch

Many registers have particular bit designated to a particular port, so that the status of each port
can be changed or monitored independently. The mapping of Register-Bit and Port-ID for each
controller is listed in Table-7.0.2.
Table-7.0.2: Register-Bit/Port-ID Mapping
Register –Bit
Port –ID
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
Port Number
ACD82224
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port 10
Port 11
Port 12
Port 13
Port 14
Port 15
Port 16
Port 17
Port 18
Port 19
Port 20
Port 21
Port 22
Port 23
INTSRC register (register 1)
The INTSRC register indicates the source of the interrupt request. Before the CPU starts to
respond to an interrupt request, it should read this register to find out the interrupt source. This
register is automatically cleared after each read. Table-7.1 lists all the bits of this register.
Table-7.1: INTSRC Register
Bit
Description
0
System initialization completed
1
System error occurred
2
Port partition occurred
3
ARL Interrupt
4
Reserved
5
6
7
Default
0
Note: The source interrupt for bit-3 ARL interrupt is referred to ARL Register-13.
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