ACD82224 Datasheet, PDF (17/77 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch

using a CPU. ACD82224 also allows the CPU to access any registers in the PHY devices
through the CPU interface.
SRAM Interface
The ACD82224 uses pipeline ZBT^TM (zero-bus- turn-around) or compatible types of SRAM. The
speed should be 100MHz or faster. Each read or write cycle should take no more than 10 ns.
The SRAM interface contains a 52-bit data bus (48-bit data and 4-bit status), a 19-bit address
bus, and 2 control signals.
CPU Interface
The ACD82224 does not require any microprocessor for operation. Initialization and most
configurations can be done with pull-up or pull-down of designated hardware pins. A CPU
interface is provided for a microprocessor to access the internal control registers and status
registers. The microprocessor can send a read command to retrieve the status of the switch, or
send a write command to configure the switch through the interface. The interface is a commonly
used UART type interface. The CPU interface can also be used to access the registers inside
each PHY device connected to the ACD82224.
ARL Interface
The ACD82224 has a built-in MAC address storage for up to 2,048 source addresses. If more
than 2,048 addresses are needed, an external ARL (e.g. ACD80800) can be used to expand the
address space to 11K entries.
The external ARL is connected through the ARL interface (Table-6.9). It can tap the value if DA
out of the memory interface bus, and execute a lookup process to map the value of the DA into a
port number. It can also learn the SA values embedded in the received frames. The value of SA
is used to build the address lookup table inside the ACD80800. If the new addressed are over the
maximum number of look-up table, ARL will not learn the newer address until there is any
available entry again (i.e. the learned address aged).
MIB Interface
Traffic activities on all ports of the ACD82224 can be monitored through the MIB interface.
Through the MIB interface, a MIB device can view the frames transmitted from or received by
any port. Therefore, the MIB device can maintain a record of traffic statistics for each port to
support network management. Since all received data are stored into the memory buffer, and all
transmitted data are retrieved from the memory buffer, the data of the activities can also be
captured from the memory interface data bus. The status of each data transaction between the
ACD82224 and SRAM is displayed by dedicated status signals of the ACD82224 interface
(Table-6.9).
LED Interface
The ACD82224 provides a wide variety of LED indicators for simple system management. The
update of the LED is completely autonomous and merely requires low speed TTL or CMOS
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