ACD82224 Datasheet, PDF (32/77 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch

BTH register (register 11)
The BTH register contains the broadcast queue buffer threshold for each port. When the upper
threshold is exceeded, the MAC may generate a Max-Pause-Frame. When the lower threshold is
crossed, the MAC may generate a Mini-Pause-Frame. Table-7.11 describes each bit in this
register.
Table-7.11: BTH Register
Bit
7:0
15:8
Description
Lower threshold of broadcast queue
Higher threshold of broadcast queue
Default
16
48
MINL & MINH register (register 12,13)
The MINL and MINH registers together contain the 32-bit Frame Check Sequence (FCS) of the
mini-pause-frame. MINL contains the least significant 16 bit of the FCS. MINH contains the most
significant 16 bit of the FCS. The default FCS value assumes the default source address for the
Mini-Pause-Frame. Table-7.12 and table-7.13 describe all the bits of these two registers.
Table-7.12: MINL Register
Bit
Description
7:0
Bit 31:24 of the mini-pause-frame’s FCS
15:8
Bit 23:16 of the mini-pause-frame’s FCS
Default
89
O3
Table-7.13: MINH Register
Bit
Description
7:0
Bit 15:18 of the mini-pause-frame’s FCS
15:8
Bit 7:0 of the mini-pause-frame’s FCS
Default
D7
A9
MAXL & MAXH register (register 14,15)
The MAXL and MAXH registers together contain the 32-bit Frame Check Sequence (FCS) of the
max-pause-frame. MAXL contains the least significant 16 bit of the FCS. MAXH contains the
most significant 16 bit of the FCS. The default FCS value assumes the default source address
for the Max-Pause-Frame. Table-7.14 and table-7.15 describe all the bits of these two registers.
Table-7.14: MAXL Register
Bit
Description
7:0
Bit 31:24 of the max-pause-frame’s FCS
15:8
Bit 23:16 of the max-pause-frame’s FCS
Table-7.15: MAXH Register
Bit
Description
7:0
Bit 15:8 of the max-pause-frame’s FCS
15:8
Bit 7:0 of the max-pause-frame’s FCS
Default
0D
68
Default
D8
D0
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