ACD82224 Datasheet, PDF (37/77 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch

Table-7.25: POSCFG Register
Bit Description
3:0 ZBT SRAM Read Timing Adjustment
(16 levels within a 10 ns clock cycle, each delay unit adds
approximately 0.5-0.7 ns, “inversion” adds 5 ns or one half of
clock cycle to the delay)
0001 – no delay
0000 – inversion plus no delay
0011 – 1 units delay 0010 – inversion plus 1 units delay
0101 – 2 units delay 0100 – inversion plus 2 units delay
0111 – 3 units delay 0110 – inversion plus 3 units delay
1001 – 4 units delay 1000 – inversion plus 4 units delay
1011 – 5 units delay 1010 – inversion plus 5 units delay
1101 – 6 units delay 1100 – inversion plus 6 units delay
1111 – 7 units delay 1110 – inversion plus 7 units delay
7:4 ZBT SRAM Clock Timing Adjustment
(16 levels within a 10 ns clock cycle, each delay unit adds
approximately 0.5-0.7 ns, “inversion” adds 5 ns or one half of
clock cycle to the delay)
0101 – no delay
0100 – inversion plus no delay
0111 – 1 units delay 0110 – inversion plus 1 units delay
0001 – 2 units delay 0000 – inversion plus 2 units delay
0011 – 3 units delay 0010 – inversion plus 3 units delay
1101 – 4 units delay 1100 – inversion plus 4 units delay
1111 – 5 units delay 1110 – inversion plus 5 units delay
1001 – 6 units delay 1000 – inversion plus 6 units delay
1011 – 7 units delay 1010 – inversion plus 7 units delay
9:8 SRAM size selection:
00 – 64K words
01 – 128K words
10 – 256k words
11 – 512K words
10 0 – MDC latched by rising edge;
1 – MDC latched by falling edge;
11 0 – Long Event defined as frame longer than 1518 byte.
1 – Long Event defined as frame longer than 1530 byte.
12 0 – Frames with unknown DA forwarded to the dumping port.
1 – Frames with unknown DA forwarded to all ports.
13
14
15
16
17
18
19
21:20
0 – Internal ARL selected (2K MAC address entry).
1 - External ARL selected (11K MAC address entry).
0 – PHY Ids start from 0, range from 1 to 23.
1 – PHY Ids start from 1, range from 0 to 24
0 – Re-transmit after excessive collision.
1 – Drop after excessive collision.
0 – Automatic PHY Management enabled
1 – Automatic PHY Management disabled: CPU need to
update SPEED, LINK, DPLX and PAUSE registers
0 – Flow Control on broadcast queue utilization enabled
1 – Flow control on broadcast queue utilization disabled:
broadcast frames dropped if the queue is full
0 – System errors will trigger software reset
1 – System errors will trigger hardware reset
0 – System will start by itself upon hardware reset
1 – System will not start until bit-5/6 of register-16 is set
2-bit device ID for UART communication. The device responses
only to UART commands with matching ID
22 0 – RMII TX’s data is driven on falling edge
1 – RMII TX’s data is driven on rising edge
23 0 – RMII RX’s data is latched on rising edge
1 – RMII RX’s data is latched on falling edge
Default
0000
0000
01
0
1
0
0
0
0
0
0
0
0
0
1
1
Shared Pin
P21TXD1
P21TXD0
P20TXD1
P20TXD0
(From Bit3
to Bit0)
P18TXD1
P18TXD0
P17TXD1
P17TXD0
P21TXEN
P20TXEN
P17TXEN
P18TXEN
LEDLCK
LEDVLD0
LEDCLD1
nLED3
nLED2
nLED1
nLED0
P15TXEN
P14TXEN
P12TXEN
P23TXEN
P11TXEN
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