ACD82224 Datasheet, PDF (16/77 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch

Spanning Tree Support
The ACD82224 supports the Spanning Tree protocol. When Spanning Tree Support is enabled
(Register-16 bit-1, see Table 7.15), frames from the CPU port (port-23) having a DA value equal
to the reserved Bridge Management Group Address for BPDU will be forwarded to the port
specified by the CPU. Frames from all other ports with a DA value equal to the Reserved Group
Address for BPDU will be forwarded to the CPU port if the port is in the same VLAN of the CPU
port. Port 23 is designed as the default CPU port. When Spanning Tree Support is disabled
(Register-22 nPORT Register), all reserved group addresses for Bridge Management is treated
as broadcast addresses, with the exception of the reserved multicast addresses for pause frame
specified by IEEE802.3x.
Every port of the ACD82224 can be set to block-and-listen mode (Register-21 nBP Register)
through the CPU interface. In this mode, incoming frames with a DA value equal to the reserved
Group Address for BPDU will be forwarded to the CPU port. Incoming frames with all other DA
values will be dropped. Outgoing frames with a DA value equal to the Group Address for BPDU
will be forwarded to the attached PHY device; all other outgoing frames will be filtered.
Queue Management
Each port of the ACD82224 has its own individual transmission queue. All frames coming into
the ACD82224 are stored into the shared memory buffer, and are lined up in the transmission
queues of the corresponding destination port. The order of all frames, unicast or broadcast, is
strictly enforced by the ACD82224. The ACD82224 is designed with a non-blocking switching
architecture. It is capable of achieving wire speed forwarding rates and can handle maximum
traffic loads.
PHY Management
The ACD82224 supports PHY device management through the serial MDIO and MDC signal
lines. The ACD82224 can continuously poll the status of the PHY devices through the serial
management interface if Register-25 bit-16 is cleared. The ACD82224 will also configure the
PHY capability field like Link, Speed, and Duplex status to ensure proper operation of the link.
The ACD82224 also enables the CPU to access any registers in the PHY devices through the
CPU interface (See Register-32 example). The ID of the PHY device can start from either “0” or
“1”, depending on the setting of bit-14 of register-25.
There are two ways to disable Automatic PHY Management as follows:
(1) Set Register-25 bit-16 to disable Automatic PHY Management for all ports.
(2) Set the specific port in Register-29 to disable the port from Automatic PHY Management.
PHY Interface
The PHY interface for port-0 through port-22 can only be RMII. The RMII CLK (50MHz clock) will
be used as the RXCLK and TXCLK. There are three wires on the receiving side (RXD[1:0] and
CRS_DV), and three wires on the transmitting side (TXD[1:0] and TXEN). Port-23 can be
configured as either RMII or MII (Register-16 bit-15). The MII option is used for direct connection
with the ACD80900 only supporting MII interface.
ACD82224 supports PHY management through the MDIO and MDC signal lines. ACD82224 can
continuously poll the status of the PHY devices through the serial management interface, without
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