ACD82224 Datasheet, PDF (34/77 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch

INTMSK register (register 17)
The INTMSK register defines the valid interrupt sources allowed to assert interrupt request pin.
Table-7.17 lists all the bits of this register.
Table-7.17: INTMSK Register
Bit
Description
0
Enable “system initialization completion” to interrupt
1
Enable “internal system error” to interrupt
2
Enable “port partition event” to interrupt
3
Enable “internal ARL” to interrupt
4
Reserved
5
6
7
Default
1
SPEED register (register 18)
The SPEED register specifies or indicates the speed rate of each port. Table-7.18 describes all
the bits of this register. These two modes are also applied to the SPEED (register-18), LINK
(register-19), DPLX (register-27), PAUSE (register-26) register.
(1) Automatic PHY management mode (default setting): These four registers controlled by
ACD82224's PHY management Hardware update their status. To enable this mode if bit-16
of register-25 is cleared, and the corresponding bit (port) in nPM register (register-29) is
cleared.
(2) CPU mode: CPU sets these registers through UART interface. To enable this mode if bit-16
of register-25 is set, or the corresponding bit (port) in nPM register (register-29) is set.
Table-7.18: SPEED Register
Bit
Description
[0:23]
0 – Port X at 10Mbps
1 – Port X at 100Mbps
Default
0
LINK register (register 19)
The LINK register specifies or indicates the link status of each port. Table-7.19 describes all the
bits of this register.
Table-7.19: LINK Register
Bit
Description
[0:23]
0 – Port X link not established
1 – Port X link established
Default
0
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