ACD82224 Datasheet, PDF (33/77 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch

SYSCFG register (register 16)
The SYSCFG register specifies certain system configurations. The system options are described
in the chapter of “Function Description.” Table-7.16 describes all the bits of this register.
Table-7.16: SYSCFG Register
Bit Description
0 0 – BIST enabled;
1 – BIST disabled.
1 0 – Spanning Tree support disabled;
1 – Spanning Tree support enabled
2 0 – External ARL result latched by rising edge;
1 – External ARL result latched by falling edge;
3
Reserved.
4
Reserved.
5 0 – wait for CPU.
1 – system ready to start
*This bit is used by the CPU when bit-15 of register-25 is set as “0” (for system
with control CPU). The system will wait for CPU to set this bit.
Must set this bit before CPU programs any register.
6 0 – PHY Management not completed
1 – PHY Management completed.
*This bit is used by the CPU when bit-15 of register-25 is set as “0” (for system
with a control CPU). The MAC will not start until this bit is set by the CPU.
7 0 – Watchdog function enabled.
1 – Watchdog function disabled.
8 0 – Secure VLAN checking rule enforced.
1 – Leaky VLAN checking rule enforced.
9
Reserved.
10 0 – Late Back-Pressure scheme disabled
1 – Late Back-Pressure scheme enabled
*When enabled, the MAC will generate back-pressure only after reading the first
bit of DA
11 0 – special handling of broadcast frames disabled
1 – special handling of broadcast frames enabled
*When enabled, all broadcast frames from Port0~Port22 are forwarded to the
Port23 only, and all broadcast frames from the Port23 are forwarded to all other
ports.
12 Software Reset: Set “1” to start a system reset to initialize all state machines.
It will not re-start PHY's Auto-Negotiation.
13 Hardware Reset: Set “1” to stop the life pulse on the watchdog pin, which in turn
will trigger the external watchdog circuitry to reset the whole system.
14
Reserved
15 0 – Port 23 is MII
1 – Port 23 is RMII (POS shared with P03TXEN)
Default
0
1
If the bit-19 of Register-25 is set (CPU start mode), ACD82224 will stop the initialized procedures
after it is completed with self-test. CPU must set bit-5 of register-16 to enable access internal
registers. CPU set bit-6 of register-16 to enable MAC and Queue manager. Then ACD82224 will
start switching based on CPU’s configuration.
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