ACD82224 Datasheet, PDF (21/77 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch

Table-6.3: PHY Management Interface Signals
Name
Type
Description
MDC
O
PHY management clock (1.25MHz)
MDIO
I/O
PHY management data
Frames transmitted on MDIO has the following format (Table-6.4):
Table-6.4: MDIO Format
Operation
PRE
ST OP PHY-ID REG-AD
TA
DATA IDLE
Write
1…1
01
01
A[4:0]
R[4:0]
10
D[15:0]
Z
Read
1…1
01
10
A[4:0]
R[4:0]
Z0
D[15:0]
Z
Prior to any transaction, the ACD82224 will output thirty-two bits of ‘1’ as preamble signal. After
the preamble, a 01 signal is used to indicate the start of the frame.
For a write operation, the device will send a ‘01’ to signal a write operation. Following the ‘01’
write signal will be the 5 bit ID address of the PHY device and the 5 bit register address. A ‘10’
turn around signal is then follows the “write” signal. After the turn around, the 16 bit of data will
be written into the register. After the completion of the write transaction, the line will be left in a
high impedance state.
For a read operation, the ACD82224 will output a ‘10’ to indicate read operation after the start of
frame indicator. Following the ‘10’ read signal will be the 5-bit ID address of the PHY device and
the 5-bit register address. Then, the ACD82224 will cease driving the MDIO line, and wait for one
bit time. During this time, the MDIO should be in a high impedance state. The ACD82224 will
then synchronize with the next bit of ‘0” driven by the PHY device, and continue on to read 16
bits of data from the PHY device.
The system designer can set the ID of the PHY devices as 0 for port-0, 1 for port-1, … and 23
for port-23, when the PHYID option (Bit-14 of Register-25) is set to “0”. If the PHYID option is set
to “1”, the corresponding PHY ID should set to 1 through 24. The detailed timing requirements on
PHY management signals are described in the chapter of “Timing Description.”
CPU Interface
The ACD82224 includes a CPU UART interface to enable an external CPU to access the internal
registers of the ACD82224. The baud rate of the UART can be from 19200 to 38400 bps. The
ACD82224 automatically detects the baud rate for each command, and returns the result at the
same baud rate. The signals in the CPU interface are described in Table-6.5.
Table-6.5: CPU Interface Signals
Name
Type
CPUDI
I
CPUDO
Tri-state
CPUIRQ
O
Description
CPU data input
CPU data output
CPU interrupt request
A command sent by the CPU through the CPUDI line consists of 7 octets. Command frames
transmitted on CPUDI have the format shown in Table-6.6:
Table-6.6: CPUDI Format
Operation
Command
Write
0010XX11
Address
A[7:0]
Index
I[7:0]
Data
D[23:0]
Checksum
C[7:0]
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