ACD82224 Datasheet, PDF (28/77 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch

7. REGISTER DESCRIPTION
Registers in the ACD82224 are used to define the operational mode of various function modules
of the switch controller and the peripheral devices. Default values at power-on are predefined.
The management CPU (optional) can read the content of all registers and modify some of the
registers to change the operational mode. Table-7.0.1 lists all the registers inside the switch
controller.
Table-7.0.1: Register List
Address
Name
0
DEVID
1
INTSRC
2
SYSERR
3
PAR
4
PMERR
5
ACT
6
RSVD
7
RSVD
8
SAL
9
SAH
10 UTH
11 BTH
12 MAXL
13 MAXH
14 MINL
15 MINH
16 SYSCFG
17 INTMSK
18 SPEED
19 LINK
20 nFWD
21 nBP
22 nPORT
23 PVID
24 VPID
25 POSCFG
26 PAUSE
27 DPLX
28 RSVD
29 nPM
30 ERRMSK
31 CLKADJ
32~63 PHYREG
Type
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Size
16 Bit
8 Bit
9 Bit
24 Bit
24 Bit
24 Bit
-
-
24 Bit
24 Bit
16 Bit
16 Bit
16 Bit
16 Bit
16 Bit
16 Bit
16 Bit
8 Bit
24 Bit
24 Bit
24 Bit
24 Bit
24 Bit
4 Bit
5 Bit
24 Bit
24 Bit
24 Bit
-
24 Bit
8 Bit
8 Bit
16 Bit
Index
1
1
1
1
1
1
-
-
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
24
4
1
1
1
-
1
1
1
32
Description
Device ID is 0601h
Interrupt Source
System Error
Port Partition Indication
PHY Management Error
Port Activity
-
-
Source Address, bit 23:0
Source Address, bit 47:24
Unicast Threshold
Broadcast Threshold
FCS of Max-Pause-Frame, bit 15:0
FCS of Max-Pause-Frame, bit 31:16
FCS of Mini-Pause-Frame, bit 15:0
FCS of Mini-Pause-Frame, bit 31:16
System Configuration
Interrupt Mask
Port Speed
Port Link
Port Forward Disable
Port Back Pressure Disable
Port Disable
Port VLAN ID
VLAN Dumping Port
Power-On-Strobe Configuration
Port Pause Frame Disable
Port Duplex Mode
-
Port PHY Management Disable
Error Mask
ARL Clock Delay Adjustment
Registers in PHY device with ID is 0~31
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