ACD82224 Datasheet, PDF (22/77 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch

Read
0010XX01
A[7:0]
I[7:0]
D[23:0]
C[7:0]
The byte order of data in all fields follows the big-endian convention, i.e. most significant octet
first. The bit order is the least significant order first. The Command octet specifies the type of the
operation.
The Bit-7, bit-6, and bit-5 of the command octet are specified the Device Type.
(1) Switch Controller, the device type is 001.
(2) ARL Controller, the device type is 010.
(3) Management Controller, the device type is 100.
The Bit-2 and bit-3 of the command octet are used to specify the device ID of the chip. They are
set by bit 20 and bit 21 of the Register 25 at power on strobe. The address octet specifies the
number of the register. The index octet specifies the index of the register in a register array.
For write operation, the Data field is a 3-octet value to specify what to write into the register. For
read operation, the Data field is a 3-octet 0 as padded data. If the data of register is less than 24-
bit, it is aligned to bit-0 of Data field.
The checksum value is an 8-bit value of exclusive-OR of all octets in the frame, starting from the
Command octet.
For each valid command received, the ACD82224 will always send a response. Response from
the ACD82224 is sent through the CPUDO line. Response frames sent by the ACD82224 have
the following format (Table-6.7):
Table-6.7: Switch Response Format
Response
Command
Write
00000011
Read
00000001
Result
R[7:0]
R[7:0]
Data
D[23:0]
D[23:0]
Checksum
C[7:0]
C[7:0]
The command octet specifies the type of the response. The result octet specifies the result of the
execution.
The Result field in a response frame is defined as:
• “0” for no error
• “1” for Access Violation Error
For response to a read operation, the Data field is a 3-octet value to indicate the content of the
register. For response to a write operation, the Data field is 32 bits of 0. If the data of register is
less than 24-bit, it is align to bit-0 of Data field.
The checksum value is an 8-bit value of exclusive-OR of all octets in the response frame,
starting from the Command octet.
CPUIRQ is high active and used to notify the CPU that some special status has been
encountered by the ACD82224, like port partition, and fatal system error, etc. By clearing the
appropriate bit in the interrupt mask register, the specific source interrupt can be stop. Reading
the interrupt source register retrieves the source of the interrupt request and clears the interrupt
source register. CPUIRQ keeps high if the interrupt source is still existed.
SRAM Interface
All received frames are stored into the shared frame buffer through the memory interface. When
the destination port is ready to transmit the frame, data is read from the shared memory buffer
through the memory interface. The memory interface signals are described in the following table:
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