OXCB950 Datasheet, PDF (9/68 Pages) List of Unclassifed Manufacturers – Integrated High Performance UART Cardbus / PCI interface

OXFORD SEMICONDUCTOR LTD.
OXCB950
Multi-purpose & External
interrupt pins
26
27
EEPROM pins
28
29
31
Dir¹
T_I/O
T_I/O
O
O
IU
30
O
Miscellaneous pins
34
ID
33
ID
Power and ground²
89, 14, 63
V
56, 71, 81, 91, 7, 21
V
38, 39
V
41,
V
62, 87, 13
G
55, 64,65,70, 76, 82, 90, 92, 97,
G
2, 6, 12, 20,
35
G
40, 50
G
Name
Description
MIO[0]
MIO[1]
Multi-purpose I/O pins.
Can be driven high or low, or be used to invoke
cardbus/PCI interrupts, and powerdown, wakeup requests.
EE_CK
EE_CS
EE_DI
EE_DO
EEPROM clock
EEPROM active-high Chip Select
EEPROM data in (to be connected to the EEPROM DO
pin).
When the optional serial EEPROM is connected, this pin
should be pulled up using an external 1-10k resistor. When
the EEPROM is not used, this external pull-up is not
required (internal pull-up is sufficient).
EEPROM data out. (to be connected to the EEPROM DI
pin)
TEST0
TEST1
Test Pin 0. Should be held low at all times.
Test Pin 1. Should be held low at all times
VDD3I_CB
VDD3OP_CB
VDDIP
VDDO
VSSI_CB
VSSOP_CB
VSSIP
VSSO
Supplies power to the pre-drive area of the dual mode
cardbus/pci IO buffers.
Supplies power to the output drive of the dual mode
cardbus/pci IO buffers.
Supplies power to the core-logic and pre-drive area of the
standard IO buffers.
Suppiles power to the output drive of standard IO buffers.
Supplies ground to the pre-drive area of the dual mode
cardbus/pci IO buffers.
Supplies ground to the output drive of the dual mode
cardbus/pci IO buffers.
Supplies gnd to the core-logic and pre-drive area of the
standard IO buffers.
Supplies gnd to the output drive of standard IO buffers.
Table: Pin Descriptions
Note 1: Direction key:
I
ID
IU
O
T_O
T_I
T_I/O
3.3v Input, TTL compatible
3.3v Input with pull-down, TTL compatible
3.3v Input with pull-up, TTL compatible
3.3v Output, TTL compatible
5.0v tolerant TTL output
5.0v tolerant TTL input
5.0v tolerant TTL Bi-directional
C/P_I Cardbus/PCI compatible input
C/P_O Cardbus/PCI compatible output
C/P_I/O Cardbus/PCI compatible bi-directional
C/P_OD Cardbus/PCI compatible open drain
G
Ground
V
3.3V power
Note 2: Power & Ground
There are several types of VDD and VSS in this design, providing not only power for the internal (core) and I/O pad area but also
special power lines to the dual mode cardbus/pci I/O buffers. These power rails are not connected internally.
This precaution reduces the effects of simultaneous switching outputs and undesirable RF radiation from the chip. Further
precaution is taken by segmenting the GND and VDD rails to isolate the PCI and UART pins.
Data Sheet Revision 1.1
Page 9