OXCB950 Datasheet, PDF (4/68 Pages) List of Unclassifed Manufacturers – Integrated High Performance UART Cardbus / PCI interface

OXFORD SEMICONDUCTOR LTD.
1 PERFORMANCE COMPARISON
OXCB950
Feature
Support for PCI Power Management
Zero wait-state read/write operation
No. of external interrupt source pins
DWORD access to UART Interrupt Source
Registers & FIFO Levels
Good-Data status
Full Plug and Play with external EEPROM
External 1x baud rate clock
Max baud rate in normal mode
Max baud rate in 1x clock mode
FIFO depth
Sleep mode
Auto Xon/Xoff flow
Auto CTS#/RTS# flow
Auto DSR#/DTR# flow
No. of Rx interrupt thresholds
No. of Tx interrupt thresholds
No. of flow control thresholds
Transmitter empty interrupt
Readable status of flow control
Readable FIFO levels
Clock prescaler options
Rx/Tx disable
Software reset
Device ID
9-bit data frames
RS485 buffer enable
Infra-red (IrDA)
OXCB950
yes
yes
2
yes
yes
yes
yes
15 Mbps
60 Mbps
128
yes
yes
yes
yes
128
128
128
yes
yes
yes
248
yes
yes
yes
yes
yes
yes
16C550 +
PLX9050
no
no
2
no
no
yes
no
115 Kbps
n/a
16
no
no
no
no
4
1
n/a
no
no
no
n/a
no
no
no
no
no
no
16C650 +
PLX9050
No
No
2
No
No
Yes
No
1.5 Mbps
n/a
64
Yes
Yes
Yes
No
4
4
4
No
No
No
2
No
No
No
No
No
Yes
Table 1: OXCB950 performance compared with PLX + generic UART combinations in PCI mode
1.1 Improvements of the OXCB950 over discrete solutions:
Improved access timing:
Access to the internal UART requires zero or one PCI wait states. A cardbus/PCI read transaction from the internal UART can
complete within five PCI clock cycles and a write transaction to the internal UART can complete within four PCI clock cycles.
Reduces interrupt latency:
The OXCB950 offers shadowed FIFO levels and Interrupt status registers of the internal UART, as well as general device
interrupt status, to reduce the device driver interrupt latency.
Power management:
The OXCB950 complies with the Cardbus Power Management Specification, given by the PC CARD standard release 7.0/7.1,
the PCI Power Management Specification 1.0 and the PC98/99 Power Management specifications, by offering the extended
capabilities for Power Management and supporting the power states D0, D2 and D3. This achieves significant power savings by
allowing device drivers to power down the cardbus/PCI function and disable the UART channel.
Data Sheet Revision 1.1
Page 4