OXCB950 Datasheet, PDF (19/68 Pages) List of Unclassifed Manufacturers – Integrated High Performance UART Cardbus / PCI interface

OXFORD SEMICONDUCTOR LTD.
OXCB950
6.4.4 Global Interrupt Status and Control Register ‘GIS’ (Offset 0x0C)
This register controls the assertion of interrupts and power management events, as well as returning the internal status of all
interrupt sources and power management events.
Bits Description
Read/Write
EEPROM _PCI
1:0 Reserved
-
R
2
MIO0 Internal State.
-
R
This bit reflects the state of the internal MIO[0] signal. The internal MIO[0]
signal reflects the non-inverted or inverted state of MIO0 pin. ²
3
MIO1 Internal State
-
R
This bit reflects the state of the internal MIO[1] signal. The internal MIO[1]
reflects the non-inverted or inverted state of MIO1 pin. ²
17-4 Reserved
-
R
18
MIO0 Interrupt Enable
W
RW
When set (1) allows the pin MIO0 to assert an interrupt on the device’s INTA#
(CINT#) pin. The state of the MIO0 signal that causes an interrupt is
dependant upon the polarity set by the register fields MIC(1:0)
19
MIO1 Interrupt Enable
W
RW
When set (1) allows the pin MIO1 to assert an interrupt on the device’s INTA#
(CINT#) pin. The state of the MIO1 signal that causes an interrupt is
dependant upon the polarity set by the register fields MIC(3:2)
20
Power-down Internal Interrupt Status.
-
R
This is a sticky bit. When set, it indicates that a power-down request has been
recognised (validated), which would normally have asserted a powerdown
interrupt on the INTA# (CINT#) pin if GIS bit 21 was set.
Reading this bit clears the Internal Powerdown Interrupt Status.
21
Power-down interrupt enable.
W
RW
When set to ‘1’, a powerdown request is allowed to generate an interrupt on
the INTA#/ (CINT# ) pin.
22
UART interrupt status^{. 1}
-
R
This bit reflects the interrupt status of the internal UART.
23
UART Interrupt Enable.
W
R/W
When set (1) allows the UART to assert an interrupt on the device’s INTA#
(CINT# ) pin ³
24
UART Power Management Event Enable
W
R/W
A value of ‘1’ enables the UART ‘wakeup’ events to set the PME_Status bit in
the PCI PMCSR register, and hence assert the PME# (pci) or CSYSCHG
(cardbus) pin if this option has been enabled.
A value of ‘0’ prevents any wakeup events from the UART from setting the
PCI PME_Status bit.
25
UART Powerdown Filter Control
W
R/W
A ‘1’ enables the UART to invoke a powerdown request via the power down
filter (if the filter is enabled).
31:24 Reserved
-
R
Reset
0x0h
X
X
0
1
1
X
0
0
1
0
0
00h
Data Sheet Revision 1.1
Page 19