OXCB950 Datasheet, PDF (54/68 Pages) List of Unclassifed Manufacturers – Integrated High Performance UART Cardbus / PCI interface

OXFORD SEMICONDUCTOR LTD.
OXCB950
8.1.5 Zone4: PCI Configuration Registers
The Zone4 region of EEPROM contains any changes
required to the PCI Configuration registers (including the
Vendor ID and Subsystem Vendor ID). This zone consists
of a function header WORD, and one or more
configuration WORDs for that function. The function header
is described in Table 26.
Bits Description
15 ‘0’ = End of Zone 4.
‘1’ = Define this function header.
14:3 Reserved. Write zeros.
2:0 Function number for the following configuration
WORD(s).
‘000’ = Function0
Other values = Reserved.
Table 26: Zone 4 data format (Function Header)
The subsequent WORDs for each function contain the
address offset and a byte of programming data for the PCI
Configuration Space belonging to the function number
selected by the proceeding Function-Header. The format of
configuration WORDs for the PCI Configuration Registers
are described below.
Bits Description
15 ‘0’ = This is the last configuration WORD in for
the selected function in the Function-Header.
‘1’ = There is another WORD to follow for this
function.
14:8 These seven bits define the byte-offset of the PCI
configuration register to be programmed. For
example the byte-offset of the Interrupt Pin
register is 0x3D. Offset values are tabulated in
section 6.2.
7:0 8-bit value of the register to be programmed
Table 27: Zone 4 data format (data)
Table 28 shows which PCI Configuration registers are
writable from the EEPROM.
Offset Bits Description
0x00 7:0 Vendor ID bits 7 to 0.
0x01 7:0 Vendor ID bits 15 to 8.
0x02 7:0 Device ID bits 7 to 0.
0x03 7:0 Device ID bits 15 to 8.
0x06 3:0 Must be ‘0000’.
0x06 4 Extended Capabilities.
0x06 7:5 Must be ‘000’.
0x09 7:0 Class Code bits 7 to 0.
0x0A 7:0 Class Code bits 15 to 8.
0x0B 7:0 Class Code bits 23 to 16.
0x2C 7:0 SubsystemVendor ID bits 7 to 0.
0x2D 7:0 SubsystemVendor ID bits 15 to 8.
0x2E 7:0 Subsystem ID bits 7 to 0.
0x2F 7:0 Subsystem ID bits 15 to 8.
0x3D 7:0 Interrupt pin.
0x42 7:0 Power Management Capabilities
bits 7 to 0.
0x43 7:0 Power Management Capabilities
bits 15 to 8.
Table 28: EEPROM-writable PCI configuration registers
Data Sheet Revision 1.1
Page 54