OXCB950 Datasheet, PDF (7/68 Pages) List of Unclassifed Manufacturers – Integrated High Performance UART Cardbus / PCI interface

OXFORD SEMICONDUCTOR LTD.
OXCB950
4 PIN DESCRIPTIONS
Cardbus/PCI bus Pins
52, 53, 54, 57, 58, 60, 61, 66,
69, 73, 74, 75, 77, 78, 79, 100,
1, 3, 4, 5, 8, 9, 10, 11, 16, 17,
18, 19, 22, 23, 24, 25
67, 80, 99, 15
88
83
93
84
85
95
98
72
96
68
Dir¹
C/P_I/O
C/P_I
CP_I
CP_I
CP_O
CP_I
CP_O
CP_O
CP_I/O
CP_O
CP_I/O
CP_I
86
CP_I
94
CP_OD
59
CP_O
51
CP_OD
32
I
Name
AD[31:0]
C/BE[3:0]#
CLK
FRAME#
DEVSEL#
IRDY#
TRDY#
STOP#
PAR
SERR#
PERR#
IDSEL
RST#
INTA# /CINT#
CSYSCHG
PME#
SLEW_RATE
Description
Multiplexed Address/Data bus.
Multiplexed Command/Byte enable.
System clock
Cycle Frame¹.
Device Select
Initiator ready
Target ready
Target Stop request
Parity
System error
Parity error
Initialisation device select
For PCI applications this pin must be connected to the IDSEL
pin on the PCI connector. For cardbus applications, there is
no IDSEL signal, so this pin must be tied to Vdd (3.3v) via a
pull-up on the board. (10K recommended).
System reset
Interrupt Pin. For both cardbus and pci applications
Power management event signal, for Cardbus applications
This pin must be No-Connect (NC) for PCI applications.
Power management event signal, for PCI applications
This pin must be No-Connect (NC) for cardbus applications.
Slew rate control for cardbus/pci outputs
For cardbus applications, this must be tied to Vdd on the
board. For PCI applications, this must be tied to Gnd on the
board.
1 _{For cardbus applications, the pin z_frame requires a pull-up (4k7) on the board. See PC Card Standard 7.0/7.1, section}
5.3.3.3.3 “pull-up resistor requirements”.
Data Sheet Revision 1.1
Page 7