OXCB950 Datasheet, PDF(26/68 Page) List of Unclassifed Manufacturers – Integrated High Performance UART Cardbus / PCI interface

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OXCB950 Datasheet, PDF (26/68 Pages) List of Unclassifed Manufacturers – Integrated High Performance UART Cardbus / PCI interface

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OXFORD SEMICONDUCTOR LTD.

6.8 Cardbus Tuple Information

The cardbus information structure exists in the PCI

configuration space at the user selectable location of either

Dword 18 or Dword 32 and can occupy the entire PCI

configuration space region from these specified locations

upto Dword 63.

By default, the Tuple information contained within the

cardbus information structure (CIS) has been hardcoded

into the device and has been designed to satisfy the

requirements for most serial port based cardbus

applications.

For those manufacturers who would prefer to utilise their

own tuple information into the cardbus information

structure, for example to change the product ID and

Manufacturers ID codes, then a facility is available that

switches tuple access from the hardcoded area to a RAM

that contains the user defined tuple information. Using the

optional EEPROM to download data into the âCIS zoneâ

results in the user defined tuple data being downloaded

into this RAM and the RAM contents being then presented

to the configuration software, once the OXCB950 device

accepts the cardbus configuration accesses.

The size of the RAM is 46 x 32bit data. This allows up to

184 bytes of Tuple information to be present in the PCI

configuration space (from Dword18 to Dword63).

By default, this RAM is set to read-only for configuration

accesses. However, it is possible to enable configuration

writes to this RAM by enabling the local configuration

downloading into the CIS zone or via transactions to this

RAM for experimentation purposes. Any new tuple data

written directly into the RAM using cardbus transactions will

not be automatically transferred to the EEPROM for

subsequent downloads. The EEPROM will need to be

updated using the controls in the local configuration

The hardcoded (default) values in the cardbus information

structure are as follows. This is the listing provided by

Microsofts Tuple Utility DTPL.exe when operating on the

Tuple information.

NOTE : For user defined tuples, the tuple

CISTPL_CONFIG_CB must indicate the cardbus status

registers to be located at the (PCI) BAR4 in the PCI

configuration space. PCI specifications define the base

addresses as BAR0 0 â BAR5. Cardbus specifications

define the base addresses as BAR1 â BAR6.

Data Sheet Revision 1.1

OXCB950

; Tuple Data for: (CISTPL_LINKTARGET)

13 03

43 49 53

; Tuple Data for: (CISTPL_MANFID)

20 04

79 02 01 00

; Tuple Data for: (CISTPL_CONFIG_CB)

04 06

03 00 05 00 00 00