LM3S2739 Datasheet, PDF (72/532 Pages) List of Unclassifed Manufacturers – Microcontroller

System Control
Register 5: Interrupt Mask Control (IMC), offset 0x054
Central location for system control interrupt masks.
Interrupt Mask Control (IMC)
Base 0x400F.E000
Offset 0x054
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
reserved
PLLLIM
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
18
17
16
RO
RO
RO
0
0
0
2
1
0
BORIM reserved
RO
R/W
RO
0
0
0
Bit/Field
31:7
6
5:2
1
0
Name
reserved
PLLLIM
reserved
BORIM
reserved
Type
RO
R/W
RO
R/W
RO
Reset
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PLL Lock Interrupt Mask
This bit specifies whether a current limit detection is promoted to a
controller interrupt. If set, an interrupt is generated if PLLLRIS in RIS
is set; otherwise, an interrupt is not generated.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Brown-Out Reset Interrupt Mask
This bit specifies whether a brown-out condition is promoted to a
controller interrupt. If set, an interrupt is generated if BORRIS is set;
otherwise, an interrupt is not generated.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
72
June 04, 2007
Preliminary