LM3S2739 Datasheet, PDF (466/532 Pages) List of Unclassifed Manufacturers – Microcontroller

Pulse Width Modulator (PWM)
Register 13: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044
Register 14: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084
Register 15: PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4
These registers control the interrupt and ADC trigger generation capabilities of the PWM generators
(PWM0INTEN controls the PWM generator 0 block, and so on). The events that can cause an
interrupt or an ADC trigger are:
■ The counter being equal to the load register
■ The counter being equal to zero
■ The counter being equal to the comparator A register while counting up
■ The counter being equal to the comparator A register while counting down
■ The counter being equal to the comparator B register while counting up
■ The counter being equal to the comparator B register while counting down
Any combination of these events can generate either an interrupt or an ADC trigger, though no
determination can be made as to the actual event that caused an ADC trigger if more than one is
specified.
()
Base 0x4002.8000
Offset
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Type
Reset
15
14
reserved
RO
RO
0
0
13
12
11
10
9
8
TrCmpBD TrCmpBU TrCmpAD TrCmpAU TrCntLoad TrCntZero
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
7
6
reserved
RO
RO
0
0
5
4
3
2
1
0
IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bit/Field
31:14
13
12
11
10
Name
reserved
TrCmpBD
TrCmpBU
TrCmpAD
TrCmpAU
Type
RO
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
When 1, a trigger pulse is output when the counter matches the
comparator B value and the counter is counting down.
When 1, a trigger pulse is output when the counter matches the
comparator B value and the counter is counting up.
When 1, a trigger pulse is output when the counter matches the
comparator A value and the counter is counting down.
When 1, a trigger pulse is output when the counter matches the
comparator A value and the counter is counting up.
466
June 04, 2007
Preliminary