LM3S2739 Datasheet, PDF (10/532 Pages) List of Unclassifed Manufacturers – Microcontroller

Table of Contents
Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 369
Figure 15-13. Slave Command Sequence ............................................................................................ 370
Figure 16-1. CAN Module Block Diagram ........................................................................................... 395
Figure 16-2. CAN Bit Time ................................................................................................................ 402
Figure 17-1. Analog Comparator Module Block Diagram ..................................................................... 438
Figure 17-2. Structure of Comparator Unit .......................................................................................... 439
Figure 17-3. Comparator Internal Reference Structure ........................................................................ 440
Figure 18-1. PWM Module Block Diagram .......................................................................................... 449
Figure 18-2. PWM Count-Down Mode ................................................................................................ 450
Figure 18-3. PWM Count-Up/Down Mode .......................................................................................... 451
Figure 18-4. PWM Generation Example In Count-Up/Down Mode ....................................................... 451
Figure 18-5. PWM Dead-Band Generator ........................................................................................... 452
Figure 19-1. QEI Block Diagram ........................................................................................................ 480
Figure 19-2. Quadrature Encoder and Velocity Predivider Operation .................................................... 482
Figure 20-1. Pin Connection Diagram ................................................................................................ 497
Figure 23-1. Load Conditions ............................................................................................................ 516
Figure 23-2. I²C Timing ..................................................................................................................... 519
Figure 23-3. Hibernation Module Timing ............................................................................................. 519
Figure 23-4. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 520
Figure 23-5. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 520
Figure 23-6. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 521
Figure 23-7. JTAG Test Clock Input Timing ......................................................................................... 522
Figure 23-8. JTAG Test Access Port (TAP) Timing .............................................................................. 522
Figure 23-9. JTAG TRST Timing ........................................................................................................ 522
Figure 23-10. External Reset Timing (RST) ........................................................................................... 523
Figure 23-11. Power-On Reset Timing ................................................................................................. 524
Figure 23-12. Brown-Out Reset Timing ................................................................................................ 524
Figure 23-13. Software Reset Timing ................................................................................................... 524
Figure 23-14. Watchdog Reset Timing ................................................................................................. 524
Figure 24-1. 100-Pin LQFP Package .................................................................................................. 525
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June 04, 2007
Preliminary