LM3S2739 Datasheet, PDF (211/532 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S2739 Microcontroller
Register 4: GPTM Control (GPTMCTL), offset 0x00C
This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer
configuration, and to enable other features such as timer stall and the output trigger. The output
trigger can be used to initiate transfers on the ADC module.
GPTM Control (GPTMCTL)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x00C
Type R/W, reset 0x0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
reserved TBPWML TBOTE reserved
Type RO
R/W
R/W
RO
Reset
0
0
0
0
11
10
TBEVENT
R/W
R/W
0
0
9
8
7
6
5
4
TBSTALL TBEN reserved TAPWML TAOTE RTCEN
R/W
R/W
RO
R/W
R/W
R/W
0
0
0
0
0
0
19
18
17
16
RO
RO
RO
RO
0
0
0
0
3
2
1
0
TAEVENT
TASTALL TAEN
R/W
R/W
R/W
R/W
0
0
0
0
Bit/Field
31:15
14
13
12
11:10
9
8
Name
reserved
TBPWML
TBOTE
reserved
TBEVENT
TBSTALL
TBEN
Type
RO
R/W
R/W
RO
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM TimerB PWM Output Level
0: Output is unaffected.
1: Output is inverted.
GPTM TimerB Output Trigger Enable
0: The output TimerB trigger is disabled.
1: The output TimerB trigger is enabled.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM TimerB Event Mode
00: Positive edge.
01: Negative edge.
10: Reserved.
11: Both edges.
GPTM TimerB Stall Enable
0: TimerB stalling is disabled.
1: TimerB stalling is enabled.
GPTM TimerB Enable
0: TimerB is disabled.
1: TimerB is enabled and begins counting or the capture logic is enabled
based on the GPTMCFG register.
June 04, 2007
211
Preliminary