LM3S2739 Datasheet, PDF (421/532 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S2739 Microcontroller
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084
The Command Mask registers specify the transfer direction and select which buffer registers are
the source or target of the data transfer.
CAN IF1 Command Mask (CANIF1CMSK)
CAN0 base: 0x4004.0000
Offset 0x024
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
WRNRD Mask
Arb Control ClrIntPnd TxRqst/NewDat DataA DataB
Type RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:8
7
6
5
Name
reserved
WRNRD
Mask
Arb
Type
RO
R/W
R/W
R/W
Reset
0x0000
0
0x0
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Write, Not Read
0: Read. Transfer the message object address specified by the CAN
Command Request (CANIFnCRQ) register to the CAN message buffer
registers (CANIFnMSK1, CANIFnMSK2, CANIFnARB1, CANIFnARB2,
CANIFnCTL, CANIFnDA1, CANIFnDA2, CANIFnDB1, and
CANIFnDB2).
1: Write. Transfer data from the message buffer registers to the message
object address specified by the CANIFnCRQ register.
Access Mask Bits
When WRNRD=1 (writes):
0: Mask bits unchanged.
1: Transfer IDMask + Dir + MXtd to message object.
When WRNRD=0 (reads):
0: Mask bits unchanged.
1: Transfer IDMask + Dir + MXtd of the message object into the
Interface Registers.
Access Arbitration Bits
When WRNRD=1 (writes):
0: Arbitration bits unchanged.
1: Transfer ID + Dir + Xtd + MsgVal to message object.
When WRNRD=0 (reads):
0: Arbitration bits unchanged.
1: Transfer ID + Dir + Xtd + MsgVal to Message Buffer Register.
June 04, 2007
421
Preliminary